Sat, 06 Aug 2011 00:02:46 +0100
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)
1.1 --- a/JTAGB.v Sun Mar 06 21:14:43 2011 +0000 1.2 +++ b/JTAGB.v Sat Aug 06 00:02:46 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : JTAGB.v
2.1 --- a/er1.v Sun Mar 06 21:14:43 2011 +0000 2.2 +++ b/er1.v Sat Aug 06 00:02:46 2011 +0100 2.3 @@ -1,18 +1,39 @@ 2.4 -// ============================================================================= 2.5 -// COPYRIGHT NOTICE 2.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 2.7 -// ALL RIGHTS RESERVED 2.8 -// This confidential and proprietary software may be used only as authorised by 2.9 -// a licensing agreement from Lattice Semiconductor Corporation. 2.10 -// The entire notice above must be reproduced on all authorized copies and 2.11 -// copies may only be made to the extent permitted by a licensing agreement from 2.12 -// Lattice Semiconductor Corporation. 2.13 +// ================================================================== 2.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 2.15 +// ------------------------------------------------------------------ 2.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 2.17 +// ALL RIGHTS RESERVED 2.18 +// ------------------------------------------------------------------ 2.19 +// 2.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 2.21 +// 2.22 +// Permission: 2.23 +// 2.24 +// Lattice Semiconductor grants permission to use this code 2.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 2.26 +// Open Source License Agreement. 2.27 +// 2.28 +// Disclaimer: 2.29 // 2.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 2.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 2.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 2.33 -// U.S.A email: techsupport@latticesemi.com 2.34 -// =============================================================================/ 2.35 +// Lattice Semiconductor provides no warranty regarding the use or 2.36 +// functionality of this code. It is the user's responsibility to 2.37 +// verify the user’s design for consistency and functionality through 2.38 +// the use of formal verification methods. 2.39 +// 2.40 +// -------------------------------------------------------------------- 2.41 +// 2.42 +// Lattice Semiconductor Corporation 2.43 +// 5555 NE Moore Court 2.44 +// Hillsboro, OR 97214 2.45 +// U.S.A 2.46 +// 2.47 +// TEL: 1-800-Lattice (USA and Canada) 2.48 +// 503-286-8001 (other locations) 2.49 +// 2.50 +// web: http://www.latticesemi.com/ 2.51 +// email: techsupport@latticesemi.com 2.52 +// 2.53 +// -------------------------------------------------------------------- 2.54 // FILE DETAILS 2.55 // Project : LatticeMico32 2.56 // File : er1.v
3.1 --- a/jtag_cores.v Sun Mar 06 21:14:43 2011 +0000 3.2 +++ b/jtag_cores.v Sat Aug 06 00:02:46 2011 +0100 3.3 @@ -1,18 +1,39 @@ 3.4 -// ============================================================================ 3.5 -// COPYRIGHT NOTICE 3.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 3.7 -// ALL RIGHTS RESERVED 3.8 -// This confidential and proprietary software may be used only as authorised by 3.9 -// a licensing agreement from Lattice Semiconductor Corporation. 3.10 -// The entire notice above must be reproduced on all authorized copies and 3.11 -// copies may only be made to the extent permitted by a licensing agreement from 3.12 -// Lattice Semiconductor Corporation. 3.13 +// ================================================================== 3.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3.15 +// ------------------------------------------------------------------ 3.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 3.17 +// ALL RIGHTS RESERVED 3.18 +// ------------------------------------------------------------------ 3.19 +// 3.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 3.21 +// 3.22 +// Permission: 3.23 +// 3.24 +// Lattice Semiconductor grants permission to use this code 3.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 3.26 +// Open Source License Agreement. 3.27 +// 3.28 +// Disclaimer: 3.29 // 3.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 3.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 3.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 3.33 -// U.S.A email: techsupport@latticesemi.com 3.34 -// ============================================================================/ 3.35 +// Lattice Semiconductor provides no warranty regarding the use or 3.36 +// functionality of this code. It is the user's responsibility to 3.37 +// verify the user’s design for consistency and functionality through 3.38 +// the use of formal verification methods. 3.39 +// 3.40 +// -------------------------------------------------------------------- 3.41 +// 3.42 +// Lattice Semiconductor Corporation 3.43 +// 5555 NE Moore Court 3.44 +// Hillsboro, OR 97214 3.45 +// U.S.A 3.46 +// 3.47 +// TEL: 1-800-Lattice (USA and Canada) 3.48 +// 503-286-8001 (other locations) 3.49 +// 3.50 +// web: http://www.latticesemi.com/ 3.51 +// email: techsupport@latticesemi.com 3.52 +// 3.53 +// -------------------------------------------------------------------- 3.54 // FILE DETAILS 3.55 // Project : LatticeMico32 3.56 // File : jtag_cores.v
4.1 --- a/jtag_lm32.v Sun Mar 06 21:14:43 2011 +0000 4.2 +++ b/jtag_lm32.v Sat Aug 06 00:02:46 2011 +0100 4.3 @@ -1,18 +1,39 @@ 4.4 -// ============================================================================= 4.5 -// COPYRIGHT NOTICE 4.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 4.7 -// ALL RIGHTS RESERVED 4.8 -// This confidential and proprietary software may be used only as authorised by 4.9 -// a licensing agreement from Lattice Semiconductor Corporation. 4.10 -// The entire notice above must be reproduced on all authorized copies and 4.11 -// copies may only be made to the extent permitted by a licensing agreement from 4.12 -// Lattice Semiconductor Corporation. 4.13 +// ================================================================== 4.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 4.15 +// ------------------------------------------------------------------ 4.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 4.17 +// ALL RIGHTS RESERVED 4.18 +// ------------------------------------------------------------------ 4.19 +// 4.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 4.21 +// 4.22 +// Permission: 4.23 +// 4.24 +// Lattice Semiconductor grants permission to use this code 4.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 4.26 +// Open Source License Agreement. 4.27 +// 4.28 +// Disclaimer: 4.29 // 4.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 4.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 4.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 4.33 -// U.S.A email: techsupport@latticesemi.com 4.34 -// =============================================================================/ 4.35 +// Lattice Semiconductor provides no warranty regarding the use or 4.36 +// functionality of this code. It is the user's responsibility to 4.37 +// verify the user’s design for consistency and functionality through 4.38 +// the use of formal verification methods. 4.39 +// 4.40 +// -------------------------------------------------------------------- 4.41 +// 4.42 +// Lattice Semiconductor Corporation 4.43 +// 5555 NE Moore Court 4.44 +// Hillsboro, OR 97214 4.45 +// U.S.A 4.46 +// 4.47 +// TEL: 1-800-Lattice (USA and Canada) 4.48 +// 503-286-8001 (other locations) 4.49 +// 4.50 +// web: http://www.latticesemi.com/ 4.51 +// email: techsupport@latticesemi.com 4.52 +// 4.53 +// -------------------------------------------------------------------- 4.54 // FILE DETAILS 4.55 // Project : LatticeMico32 4.56 // File : jtag_lm32.v
5.1 --- a/lm32_adder.v Sun Mar 06 21:14:43 2011 +0000 5.2 +++ b/lm32_adder.v Sat Aug 06 00:02:46 2011 +0100 5.3 @@ -1,18 +1,39 @@ 5.4 -// ============================================================================= 5.5 -// COPYRIGHT NOTICE 5.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 5.7 -// ALL RIGHTS RESERVED 5.8 -// This confidential and proprietary software may be used only as authorised by 5.9 -// a licensing agreement from Lattice Semiconductor Corporation. 5.10 -// The entire notice above must be reproduced on all authorized copies and 5.11 -// copies may only be made to the extent permitted by a licensing agreement from 5.12 -// Lattice Semiconductor Corporation. 5.13 +// ================================================================== 5.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 5.15 +// ------------------------------------------------------------------ 5.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 5.17 +// ALL RIGHTS RESERVED 5.18 +// ------------------------------------------------------------------ 5.19 +// 5.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 5.21 +// 5.22 +// Permission: 5.23 +// 5.24 +// Lattice Semiconductor grants permission to use this code 5.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 5.26 +// Open Source License Agreement. 5.27 +// 5.28 +// Disclaimer: 5.29 // 5.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 5.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 5.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 5.33 -// U.S.A email: techsupport@latticesemi.com 5.34 -// ============================================================================/ 5.35 +// Lattice Semiconductor provides no warranty regarding the use or 5.36 +// functionality of this code. It is the user's responsibility to 5.37 +// verify the user’s design for consistency and functionality through 5.38 +// the use of formal verification methods. 5.39 +// 5.40 +// -------------------------------------------------------------------- 5.41 +// 5.42 +// Lattice Semiconductor Corporation 5.43 +// 5555 NE Moore Court 5.44 +// Hillsboro, OR 97214 5.45 +// U.S.A 5.46 +// 5.47 +// TEL: 1-800-Lattice (USA and Canada) 5.48 +// 503-286-8001 (other locations) 5.49 +// 5.50 +// web: http://www.latticesemi.com/ 5.51 +// email: techsupport@latticesemi.com 5.52 +// 5.53 +// -------------------------------------------------------------------- 5.54 // FILE DETAILS 5.55 // Project : LatticeMico32 5.56 // File : lm32_adder.v
6.1 --- a/lm32_addsub.v Sun Mar 06 21:14:43 2011 +0000 6.2 +++ b/lm32_addsub.v Sat Aug 06 00:02:46 2011 +0100 6.3 @@ -1,18 +1,39 @@ 6.4 -// ============================================================================= 6.5 -// COPYRIGHT NOTICE 6.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 6.7 -// ALL RIGHTS RESERVED 6.8 -// This confidential and proprietary software may be used only as authorised by 6.9 -// a licensing agreement from Lattice Semiconductor Corporation. 6.10 -// The entire notice above must be reproduced on all authorized copies and 6.11 -// copies may only be made to the extent permitted by a licensing agreement from 6.12 -// Lattice Semiconductor Corporation. 6.13 +// ================================================================== 6.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 6.15 +// ------------------------------------------------------------------ 6.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 6.17 +// ALL RIGHTS RESERVED 6.18 +// ------------------------------------------------------------------ 6.19 +// 6.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 6.21 +// 6.22 +// Permission: 6.23 +// 6.24 +// Lattice Semiconductor grants permission to use this code 6.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 6.26 +// Open Source License Agreement. 6.27 +// 6.28 +// Disclaimer: 6.29 // 6.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 6.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 6.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 6.33 -// U.S.A email: techsupport@latticesemi.com 6.34 -// =============================================================================/ 6.35 +// Lattice Semiconductor provides no warranty regarding the use or 6.36 +// functionality of this code. It is the user's responsibility to 6.37 +// verify the user’s design for consistency and functionality through 6.38 +// the use of formal verification methods. 6.39 +// 6.40 +// -------------------------------------------------------------------- 6.41 +// 6.42 +// Lattice Semiconductor Corporation 6.43 +// 5555 NE Moore Court 6.44 +// Hillsboro, OR 97214 6.45 +// U.S.A 6.46 +// 6.47 +// TEL: 1-800-Lattice (USA and Canada) 6.48 +// 503-286-8001 (other locations) 6.49 +// 6.50 +// web: http://www.latticesemi.com/ 6.51 +// email: techsupport@latticesemi.com 6.52 +// 6.53 +// -------------------------------------------------------------------- 6.54 // FILE DETAILS 6.55 // Project : LatticeMico32 6.56 // File : lm32_addsub.v
7.1 --- a/lm32_cpu.v Sun Mar 06 21:14:43 2011 +0000 7.2 +++ b/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 7.3 @@ -1,24 +1,50 @@ 7.4 -// ============================================================================= 7.5 -// COPYRIGHT NOTICE 7.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 7.7 -// ALL RIGHTS RESERVED 7.8 -// This confidential and proprietary software may be used only as authorised by 7.9 -// a licensing agreement from Lattice Semiconductor Corporation. 7.10 -// The entire notice above must be reproduced on all authorized copies and 7.11 -// copies may only be made to the extent permitted by a licensing agreement from 7.12 -// Lattice Semiconductor Corporation. 7.13 +// ================================================================== 7.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 7.15 +// ------------------------------------------------------------------ 7.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 7.17 +// ALL RIGHTS RESERVED 7.18 +// ------------------------------------------------------------------ 7.19 +// 7.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 7.21 +// 7.22 +// Permission: 7.23 +// 7.24 +// Lattice Semiconductor grants permission to use this code 7.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 7.26 +// Open Source License Agreement. 7.27 +// 7.28 +// Disclaimer: 7.29 // 7.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 7.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 7.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 7.33 -// U.S.A email: techsupport@latticesemi.com 7.34 -// =============================================================================/ 7.35 +// Lattice Semiconductor provides no warranty regarding the use or 7.36 +// functionality of this code. It is the user's responsibility to 7.37 +// verify the user’s design for consistency and functionality through 7.38 +// the use of formal verification methods. 7.39 +// 7.40 +// -------------------------------------------------------------------- 7.41 +// 7.42 +// Lattice Semiconductor Corporation 7.43 +// 5555 NE Moore Court 7.44 +// Hillsboro, OR 97214 7.45 +// U.S.A 7.46 +// 7.47 +// TEL: 1-800-Lattice (USA and Canada) 7.48 +// 503-286-8001 (other locations) 7.49 +// 7.50 +// web: http://www.latticesemi.com/ 7.51 +// email: techsupport@latticesemi.com 7.52 +// 7.53 +// -------------------------------------------------------------------- 7.54 // FILE DETAILS 7.55 // Project : LatticeMico32 7.56 // File : lm32_cpu.v 7.57 // Title : Top-level of CPU. 7.58 // Dependencies : lm32_include.v 7.59 // 7.60 +// Version 3.8 7.61 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO. 7.62 +// 2. Bug: EA now reports instruction that caused the data abort, rather than 7.63 +// next instruction. 7.64 +// 7.65 // Version 3.4 7.66 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 7.67 // never serviced. 7.68 @@ -75,6 +101,11 @@ 7.69 clk_n_i, 7.70 `endif 7.71 rst_i, 7.72 +`ifdef CFG_DEBUG_ENABLED 7.73 + `ifdef CFG_ALTERNATE_EBA 7.74 + at_debug, 7.75 + `endif 7.76 +`endif 7.77 // From external devices 7.78 `ifdef CFG_INTERRUPTS_ENABLED 7.79 interrupt_n, 7.80 @@ -212,6 +243,12 @@ 7.81 `endif 7.82 input rst_i; // Reset 7.83 7.84 +`ifdef CFG_DEBUG_ENABLED 7.85 + `ifdef CFG_ALTERNATE_EBA 7.86 + input at_debug; // GPIO input that maps EBA to DEBA 7.87 + `endif 7.88 +`endif 7.89 + 7.90 `ifdef CFG_INTERRUPTS_ENABLED 7.91 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 7.92 `endif 7.93 @@ -751,6 +788,11 @@ 7.94 // ----- Inputs ------- 7.95 .clk_i (clk_i), 7.96 .rst_i (rst_i), 7.97 +`ifdef CFG_DEBUG_ENABLED 7.98 + `ifdef CFG_ALTERNATE_EBA 7.99 + .at_debug (at_debug), 7.100 + `endif 7.101 +`endif 7.102 // From pipeline 7.103 .stall_a (stall_a), 7.104 .stall_f (stall_f), 7.105 @@ -1256,15 +1298,15 @@ 7.106 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.107 if (rst_i == `TRUE) 7.108 begin 7.109 - regfile_raw_0 <= 1'b0; 7.110 - regfile_raw_1 <= 1'b0; 7.111 - w_result_d <= 32'b0; 7.112 + regfile_raw_0 <= #1 1'b0; 7.113 + regfile_raw_1 <= #1 1'b0; 7.114 + w_result_d <= #1 32'b0; 7.115 end 7.116 else 7.117 begin 7.118 - regfile_raw_0 <= regfile_raw_0_nxt; 7.119 - regfile_raw_1 <= regfile_raw_1_nxt; 7.120 - w_result_d <= w_result; 7.121 + regfile_raw_0 <= #1 regfile_raw_0_nxt; 7.122 + regfile_raw_1 <= #1 regfile_raw_1_nxt; 7.123 + w_result_d <= #1 w_result; 7.124 end 7.125 7.126 /*---------------------------------------------------------------------- 7.127 @@ -2090,14 +2132,14 @@ 7.128 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.129 begin 7.130 if (rst_i == `TRUE) 7.131 - eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 7.132 + eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 7.133 else 7.134 begin 7.135 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 7.136 - eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.137 + eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.138 `ifdef CFG_HW_DEBUG_ENABLED 7.139 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 7.140 - eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.141 + eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.142 `endif 7.143 end 7.144 end 7.145 @@ -2107,14 +2149,14 @@ 7.146 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.147 begin 7.148 if (rst_i == `TRUE) 7.149 - deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 7.150 + deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 7.151 else 7.152 begin 7.153 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 7.154 - deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.155 + deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.156 `ifdef CFG_HW_DEBUG_ENABLED 7.157 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 7.158 - deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.159 + deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.160 `endif 7.161 end 7.162 end 7.163 @@ -2125,9 +2167,9 @@ 7.164 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.165 begin 7.166 if (rst_i == `TRUE) 7.167 - cc <= {`LM32_WORD_WIDTH{1'b0}}; 7.168 + cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.169 else 7.170 - cc <= cc + 1'b1; 7.171 + cc <= #1 cc + 1'b1; 7.172 end 7.173 `endif 7.174 7.175 @@ -2136,15 +2178,15 @@ 7.176 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.177 begin 7.178 if (rst_i == `TRUE) 7.179 - data_bus_error_seen <= `FALSE; 7.180 + data_bus_error_seen <= #1 `FALSE; 7.181 else 7.182 begin 7.183 // Set flag when bus error is detected 7.184 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 7.185 - data_bus_error_seen <= `TRUE; 7.186 + data_bus_error_seen <= #1 `TRUE; 7.187 // Clear flag when exception is taken 7.188 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 7.189 - data_bus_error_seen <= `FALSE; 7.190 + data_bus_error_seen <= #1 `FALSE; 7.191 end 7.192 end 7.193 `endif 7.194 @@ -2195,48 +2237,48 @@ 7.195 begin 7.196 if (rst_i == `TRUE) 7.197 begin 7.198 - valid_f <= `FALSE; 7.199 - valid_d <= `FALSE; 7.200 - valid_x <= `FALSE; 7.201 - valid_m <= `FALSE; 7.202 - valid_w <= `FALSE; 7.203 + valid_f <= #1 `FALSE; 7.204 + valid_d <= #1 `FALSE; 7.205 + valid_x <= #1 `FALSE; 7.206 + valid_m <= #1 `FALSE; 7.207 + valid_w <= #1 `FALSE; 7.208 end 7.209 else 7.210 begin 7.211 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 7.212 `ifdef LM32_CACHE_ENABLED 7.213 - valid_f <= valid_a; 7.214 + valid_f <= #1 valid_a; 7.215 `else 7.216 - valid_f <= `TRUE; 7.217 + valid_f <= #1 `TRUE; 7.218 `endif 7.219 else if (stall_f == `FALSE) 7.220 - valid_f <= `FALSE; 7.221 + valid_f <= #1 `FALSE; 7.222 7.223 if (kill_d == `TRUE) 7.224 - valid_d <= `FALSE; 7.225 + valid_d <= #1 `FALSE; 7.226 else if (stall_f == `FALSE) 7.227 - valid_d <= valid_f & !kill_f; 7.228 + valid_d <= #1 valid_f & !kill_f; 7.229 else if (stall_d == `FALSE) 7.230 - valid_d <= `FALSE; 7.231 + valid_d <= #1 `FALSE; 7.232 7.233 if (stall_d == `FALSE) 7.234 - valid_x <= valid_d & !kill_d; 7.235 + valid_x <= #1 valid_d & !kill_d; 7.236 else if (kill_x == `TRUE) 7.237 - valid_x <= `FALSE; 7.238 + valid_x <= #1 `FALSE; 7.239 else if (stall_x == `FALSE) 7.240 - valid_x <= `FALSE; 7.241 + valid_x <= #1 `FALSE; 7.242 7.243 if (kill_m == `TRUE) 7.244 - valid_m <= `FALSE; 7.245 + valid_m <= #1 `FALSE; 7.246 else if (stall_x == `FALSE) 7.247 - valid_m <= valid_x & !kill_x; 7.248 + valid_m <= #1 valid_x & !kill_x; 7.249 else if (stall_m == `FALSE) 7.250 - valid_m <= `FALSE; 7.251 + valid_m <= #1 `FALSE; 7.252 7.253 if (stall_m == `FALSE) 7.254 - valid_w <= valid_m & !kill_m; 7.255 + valid_w <= #1 valid_m & !kill_m; 7.256 else 7.257 - valid_w <= `FALSE; 7.258 + valid_w <= #1 `FALSE; 7.259 end 7.260 end 7.261 7.262 @@ -2246,113 +2288,113 @@ 7.263 if (rst_i == `TRUE) 7.264 begin 7.265 `ifdef CFG_USER_ENABLED 7.266 - user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 7.267 + user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 7.268 `endif 7.269 - operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.270 - operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.271 - store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.272 - branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.273 - x_result_sel_csr_x <= `FALSE; 7.274 + operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.275 + operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.276 + store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.277 + branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.278 + x_result_sel_csr_x <= #1 `FALSE; 7.279 `ifdef LM32_MC_ARITHMETIC_ENABLED 7.280 - x_result_sel_mc_arith_x <= `FALSE; 7.281 + x_result_sel_mc_arith_x <= #1 `FALSE; 7.282 `endif 7.283 `ifdef LM32_NO_BARREL_SHIFT 7.284 - x_result_sel_shift_x <= `FALSE; 7.285 + x_result_sel_shift_x <= #1 `FALSE; 7.286 `endif 7.287 `ifdef CFG_SIGN_EXTEND_ENABLED 7.288 - x_result_sel_sext_x <= `FALSE; 7.289 + x_result_sel_sext_x <= #1 `FALSE; 7.290 `endif 7.291 - x_result_sel_logic_x <= `FALSE; 7.292 + x_result_sel_logic_x <= #1 `FALSE; 7.293 `ifdef CFG_USER_ENABLED 7.294 - x_result_sel_user_x <= `FALSE; 7.295 + x_result_sel_user_x <= #1 `FALSE; 7.296 `endif 7.297 - x_result_sel_add_x <= `FALSE; 7.298 - m_result_sel_compare_x <= `FALSE; 7.299 + x_result_sel_add_x <= #1 `FALSE; 7.300 + m_result_sel_compare_x <= #1 `FALSE; 7.301 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.302 - m_result_sel_shift_x <= `FALSE; 7.303 + m_result_sel_shift_x <= #1 `FALSE; 7.304 `endif 7.305 - w_result_sel_load_x <= `FALSE; 7.306 + w_result_sel_load_x <= #1 `FALSE; 7.307 `ifdef CFG_PL_MULTIPLY_ENABLED 7.308 - w_result_sel_mul_x <= `FALSE; 7.309 + w_result_sel_mul_x <= #1 `FALSE; 7.310 `endif 7.311 - x_bypass_enable_x <= `FALSE; 7.312 - m_bypass_enable_x <= `FALSE; 7.313 - write_enable_x <= `FALSE; 7.314 - write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.315 - csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 7.316 - load_x <= `FALSE; 7.317 - store_x <= `FALSE; 7.318 - size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 7.319 - sign_extend_x <= `FALSE; 7.320 - adder_op_x <= `FALSE; 7.321 - adder_op_x_n <= `FALSE; 7.322 - logic_op_x <= 4'h0; 7.323 + x_bypass_enable_x <= #1 `FALSE; 7.324 + m_bypass_enable_x <= #1 `FALSE; 7.325 + write_enable_x <= #1 `FALSE; 7.326 + write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.327 + csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 7.328 + load_x <= #1 `FALSE; 7.329 + store_x <= #1 `FALSE; 7.330 + size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 7.331 + sign_extend_x <= #1 `FALSE; 7.332 + adder_op_x <= #1 `FALSE; 7.333 + adder_op_x_n <= #1 `FALSE; 7.334 + logic_op_x <= #1 4'h0; 7.335 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.336 - direction_x <= `FALSE; 7.337 + direction_x <= #1 `FALSE; 7.338 `endif 7.339 `ifdef CFG_ROTATE_ENABLED 7.340 - rotate_x <= `FALSE; 7.341 + rotate_x <= #1 `FALSE; 7.342 7.343 `endif 7.344 - branch_x <= `FALSE; 7.345 - branch_predict_x <= `FALSE; 7.346 - branch_predict_taken_x <= `FALSE; 7.347 - condition_x <= `LM32_CONDITION_U1; 7.348 + branch_x <= #1 `FALSE; 7.349 + branch_predict_x <= #1 `FALSE; 7.350 + branch_predict_taken_x <= #1 `FALSE; 7.351 + condition_x <= #1 `LM32_CONDITION_U1; 7.352 `ifdef CFG_DEBUG_ENABLED 7.353 - break_x <= `FALSE; 7.354 + break_x <= #1 `FALSE; 7.355 `endif 7.356 - scall_x <= `FALSE; 7.357 - eret_x <= `FALSE; 7.358 + scall_x <= #1 `FALSE; 7.359 + eret_x <= #1 `FALSE; 7.360 `ifdef CFG_DEBUG_ENABLED 7.361 - bret_x <= `FALSE; 7.362 + bret_x <= #1 `FALSE; 7.363 `endif 7.364 `ifdef CFG_BUS_ERRORS_ENABLED 7.365 - bus_error_x <= `FALSE; 7.366 - data_bus_error_exception_m <= `FALSE; 7.367 + bus_error_x <= #1 `FALSE; 7.368 + data_bus_error_exception_m <= #1 `FALSE; 7.369 `endif 7.370 - csr_write_enable_x <= `FALSE; 7.371 - operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.372 - branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.373 - m_result_sel_compare_m <= `FALSE; 7.374 + csr_write_enable_x <= #1 `FALSE; 7.375 + operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.376 + branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.377 + m_result_sel_compare_m <= #1 `FALSE; 7.378 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.379 - m_result_sel_shift_m <= `FALSE; 7.380 + m_result_sel_shift_m <= #1 `FALSE; 7.381 `endif 7.382 - w_result_sel_load_m <= `FALSE; 7.383 + w_result_sel_load_m <= #1 `FALSE; 7.384 `ifdef CFG_PL_MULTIPLY_ENABLED 7.385 - w_result_sel_mul_m <= `FALSE; 7.386 + w_result_sel_mul_m <= #1 `FALSE; 7.387 `endif 7.388 - m_bypass_enable_m <= `FALSE; 7.389 - branch_m <= `FALSE; 7.390 - branch_predict_m <= `FALSE; 7.391 - branch_predict_taken_m <= `FALSE; 7.392 - exception_m <= `FALSE; 7.393 - load_m <= `FALSE; 7.394 - store_m <= `FALSE; 7.395 - write_enable_m <= `FALSE; 7.396 - write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.397 - condition_met_m <= `FALSE; 7.398 + m_bypass_enable_m <= #1 `FALSE; 7.399 + branch_m <= #1 `FALSE; 7.400 + branch_predict_m <= #1 `FALSE; 7.401 + branch_predict_taken_m <= #1 `FALSE; 7.402 + exception_m <= #1 `FALSE; 7.403 + load_m <= #1 `FALSE; 7.404 + store_m <= #1 `FALSE; 7.405 + write_enable_m <= #1 `FALSE; 7.406 + write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.407 + condition_met_m <= #1 `FALSE; 7.408 `ifdef CFG_DCACHE_ENABLED 7.409 - dflush_m <= `FALSE; 7.410 + dflush_m <= #1 `FALSE; 7.411 `endif 7.412 `ifdef CFG_DEBUG_ENABLED 7.413 - debug_exception_m <= `FALSE; 7.414 - non_debug_exception_m <= `FALSE; 7.415 + debug_exception_m <= #1 `FALSE; 7.416 + non_debug_exception_m <= #1 `FALSE; 7.417 `endif 7.418 - operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 7.419 - w_result_sel_load_w <= `FALSE; 7.420 + operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.421 + w_result_sel_load_w <= #1 `FALSE; 7.422 `ifdef CFG_PL_MULTIPLY_ENABLED 7.423 - w_result_sel_mul_w <= `FALSE; 7.424 + w_result_sel_mul_w <= #1 `FALSE; 7.425 `endif 7.426 - write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.427 - write_enable_w <= `FALSE; 7.428 + write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.429 + write_enable_w <= #1 `FALSE; 7.430 `ifdef CFG_DEBUG_ENABLED 7.431 - debug_exception_w <= `FALSE; 7.432 - non_debug_exception_w <= `FALSE; 7.433 + debug_exception_w <= #1 `FALSE; 7.434 + non_debug_exception_w <= #1 `FALSE; 7.435 `else 7.436 - exception_w <= `FALSE; 7.437 + exception_w <= #1 `FALSE; 7.438 `endif 7.439 `ifdef CFG_BUS_ERRORS_ENABLED 7.440 - memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 7.441 + memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 7.442 `endif 7.443 end 7.444 else 7.445 @@ -2362,105 +2404,105 @@ 7.446 if (stall_x == `FALSE) 7.447 begin 7.448 `ifdef CFG_USER_ENABLED 7.449 - user_opcode <= user_opcode_d; 7.450 + user_opcode <= #1 user_opcode_d; 7.451 `endif 7.452 - operand_0_x <= d_result_0; 7.453 - operand_1_x <= d_result_1; 7.454 - store_operand_x <= bypass_data_1; 7.455 - branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 7.456 - x_result_sel_csr_x <= x_result_sel_csr_d; 7.457 + operand_0_x <= #1 d_result_0; 7.458 + operand_1_x <= #1 d_result_1; 7.459 + store_operand_x <= #1 bypass_data_1; 7.460 + branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 7.461 + x_result_sel_csr_x <= #1 x_result_sel_csr_d; 7.462 `ifdef LM32_MC_ARITHMETIC_ENABLED 7.463 - x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 7.464 + x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 7.465 `endif 7.466 `ifdef LM32_NO_BARREL_SHIFT 7.467 - x_result_sel_shift_x <= x_result_sel_shift_d; 7.468 + x_result_sel_shift_x <= #1 x_result_sel_shift_d; 7.469 `endif 7.470 `ifdef CFG_SIGN_EXTEND_ENABLED 7.471 - x_result_sel_sext_x <= x_result_sel_sext_d; 7.472 + x_result_sel_sext_x <= #1 x_result_sel_sext_d; 7.473 `endif 7.474 - x_result_sel_logic_x <= x_result_sel_logic_d; 7.475 + x_result_sel_logic_x <= #1 x_result_sel_logic_d; 7.476 `ifdef CFG_USER_ENABLED 7.477 - x_result_sel_user_x <= x_result_sel_user_d; 7.478 + x_result_sel_user_x <= #1 x_result_sel_user_d; 7.479 `endif 7.480 - x_result_sel_add_x <= x_result_sel_add_d; 7.481 - m_result_sel_compare_x <= m_result_sel_compare_d; 7.482 + x_result_sel_add_x <= #1 x_result_sel_add_d; 7.483 + m_result_sel_compare_x <= #1 m_result_sel_compare_d; 7.484 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.485 - m_result_sel_shift_x <= m_result_sel_shift_d; 7.486 + m_result_sel_shift_x <= #1 m_result_sel_shift_d; 7.487 `endif 7.488 - w_result_sel_load_x <= w_result_sel_load_d; 7.489 + w_result_sel_load_x <= #1 w_result_sel_load_d; 7.490 `ifdef CFG_PL_MULTIPLY_ENABLED 7.491 - w_result_sel_mul_x <= w_result_sel_mul_d; 7.492 + w_result_sel_mul_x <= #1 w_result_sel_mul_d; 7.493 `endif 7.494 - x_bypass_enable_x <= x_bypass_enable_d; 7.495 - m_bypass_enable_x <= m_bypass_enable_d; 7.496 - load_x <= load_d; 7.497 - store_x <= store_d; 7.498 - branch_x <= branch_d; 7.499 - branch_predict_x <= branch_predict_d; 7.500 - branch_predict_taken_x <= branch_predict_taken_d; 7.501 - write_idx_x <= write_idx_d; 7.502 - csr_x <= csr_d; 7.503 - size_x <= size_d; 7.504 - sign_extend_x <= sign_extend_d; 7.505 - adder_op_x <= adder_op_d; 7.506 - adder_op_x_n <= ~adder_op_d; 7.507 - logic_op_x <= logic_op_d; 7.508 + x_bypass_enable_x <= #1 x_bypass_enable_d; 7.509 + m_bypass_enable_x <= #1 m_bypass_enable_d; 7.510 + load_x <= #1 load_d; 7.511 + store_x <= #1 store_d; 7.512 + branch_x <= #1 branch_d; 7.513 + branch_predict_x <= #1 branch_predict_d; 7.514 + branch_predict_taken_x <= #1 branch_predict_taken_d; 7.515 + write_idx_x <= #1 write_idx_d; 7.516 + csr_x <= #1 csr_d; 7.517 + size_x <= #1 size_d; 7.518 + sign_extend_x <= #1 sign_extend_d; 7.519 + adder_op_x <= #1 adder_op_d; 7.520 + adder_op_x_n <= #1 ~adder_op_d; 7.521 + logic_op_x <= #1 logic_op_d; 7.522 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.523 - direction_x <= direction_d; 7.524 + direction_x <= #1 direction_d; 7.525 `endif 7.526 `ifdef CFG_ROTATE_ENABLED 7.527 - rotate_x <= rotate_d; 7.528 + rotate_x <= #1 rotate_d; 7.529 `endif 7.530 - condition_x <= condition_d; 7.531 - csr_write_enable_x <= csr_write_enable_d; 7.532 + condition_x <= #1 condition_d; 7.533 + csr_write_enable_x <= #1 csr_write_enable_d; 7.534 `ifdef CFG_DEBUG_ENABLED 7.535 - break_x <= break_d; 7.536 + break_x <= #1 break_d; 7.537 `endif 7.538 - scall_x <= scall_d; 7.539 + scall_x <= #1 scall_d; 7.540 `ifdef CFG_BUS_ERRORS_ENABLED 7.541 - bus_error_x <= bus_error_d; 7.542 + bus_error_x <= #1 bus_error_d; 7.543 `endif 7.544 - eret_x <= eret_d; 7.545 + eret_x <= #1 eret_d; 7.546 `ifdef CFG_DEBUG_ENABLED 7.547 - bret_x <= bret_d; 7.548 + bret_x <= #1 bret_d; 7.549 `endif 7.550 - write_enable_x <= write_enable_d; 7.551 + write_enable_x <= #1 write_enable_d; 7.552 end 7.553 7.554 // X/M stage registers 7.555 7.556 if (stall_m == `FALSE) 7.557 begin 7.558 - operand_m <= x_result; 7.559 - m_result_sel_compare_m <= m_result_sel_compare_x; 7.560 + operand_m <= #1 x_result; 7.561 + m_result_sel_compare_m <= #1 m_result_sel_compare_x; 7.562 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.563 - m_result_sel_shift_m <= m_result_sel_shift_x; 7.564 + m_result_sel_shift_m <= #1 m_result_sel_shift_x; 7.565 `endif 7.566 if (exception_x == `TRUE) 7.567 begin 7.568 - w_result_sel_load_m <= `FALSE; 7.569 + w_result_sel_load_m <= #1 `FALSE; 7.570 `ifdef CFG_PL_MULTIPLY_ENABLED 7.571 - w_result_sel_mul_m <= `FALSE; 7.572 + w_result_sel_mul_m <= #1 `FALSE; 7.573 `endif 7.574 end 7.575 else 7.576 begin 7.577 - w_result_sel_load_m <= w_result_sel_load_x; 7.578 + w_result_sel_load_m <= #1 w_result_sel_load_x; 7.579 `ifdef CFG_PL_MULTIPLY_ENABLED 7.580 - w_result_sel_mul_m <= w_result_sel_mul_x; 7.581 + w_result_sel_mul_m <= #1 w_result_sel_mul_x; 7.582 `endif 7.583 end 7.584 - m_bypass_enable_m <= m_bypass_enable_x; 7.585 + m_bypass_enable_m <= #1 m_bypass_enable_x; 7.586 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.587 `endif 7.588 - load_m <= load_x; 7.589 - store_m <= store_x; 7.590 + load_m <= #1 load_x; 7.591 + store_m <= #1 store_x; 7.592 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.593 - branch_m <= branch_x && !branch_taken_x; 7.594 + branch_m <= #1 branch_x && !branch_taken_x; 7.595 `else 7.596 - branch_m <= branch_x; 7.597 - branch_predict_m <= branch_predict_x; 7.598 - branch_predict_taken_m <= branch_predict_taken_x; 7.599 + branch_m <= #1 branch_x; 7.600 + branch_predict_m <= #1 branch_predict_x; 7.601 + branch_predict_taken_m <= #1 branch_predict_taken_x; 7.602 `endif 7.603 `ifdef CFG_DEBUG_ENABLED 7.604 // Data bus errors are generated by the wishbone and are 7.605 @@ -2469,45 +2511,48 @@ 7.606 // in same cycle (causing a debug exception). Handle non 7.607 // -debug exception first! 7.608 if (non_debug_exception_x == `TRUE) 7.609 - write_idx_m <= `LM32_EA_REG; 7.610 + write_idx_m <= #1 `LM32_EA_REG; 7.611 else if (debug_exception_x == `TRUE) 7.612 - write_idx_m <= `LM32_BA_REG; 7.613 + write_idx_m <= #1 `LM32_BA_REG; 7.614 else 7.615 - write_idx_m <= write_idx_x; 7.616 + write_idx_m <= #1 write_idx_x; 7.617 `else 7.618 if (exception_x == `TRUE) 7.619 - write_idx_m <= `LM32_EA_REG; 7.620 + write_idx_m <= #1 `LM32_EA_REG; 7.621 else 7.622 - write_idx_m <= write_idx_x; 7.623 + write_idx_m <= #1 write_idx_x; 7.624 `endif 7.625 - condition_met_m <= condition_met_x; 7.626 + condition_met_m <= #1 condition_met_x; 7.627 `ifdef CFG_DEBUG_ENABLED 7.628 if (exception_x == `TRUE) 7.629 if ((dc_re == `TRUE) 7.630 + `ifdef CFG_ALTERNATE_EBA 7.631 + || (at_debug == `TRUE) 7.632 + `endif 7.633 || ((debug_exception_x == `TRUE) 7.634 && (non_debug_exception_x == `FALSE))) 7.635 - branch_target_m <= {deba, eid_x, {3{1'b0}}}; 7.636 + branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 7.637 else 7.638 - branch_target_m <= {eba, eid_x, {3{1'b0}}}; 7.639 + branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 7.640 else 7.641 - branch_target_m <= branch_target_x; 7.642 + branch_target_m <= #1 branch_target_x; 7.643 `else 7.644 - branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 7.645 + branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 7.646 `endif 7.647 `ifdef CFG_TRACE_ENABLED 7.648 - eid_m <= eid_x; 7.649 + eid_m <= #1 eid_x; 7.650 `endif 7.651 `ifdef CFG_DCACHE_ENABLED 7.652 - dflush_m <= dflush_x; 7.653 + dflush_m <= #1 dflush_x; 7.654 `endif 7.655 - eret_m <= eret_q_x; 7.656 + eret_m <= #1 eret_q_x; 7.657 `ifdef CFG_DEBUG_ENABLED 7.658 - bret_m <= bret_q_x; 7.659 + bret_m <= #1 bret_q_x; 7.660 `endif 7.661 - write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 7.662 + write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 7.663 `ifdef CFG_DEBUG_ENABLED 7.664 - debug_exception_m <= debug_exception_x; 7.665 - non_debug_exception_m <= non_debug_exception_x; 7.666 + debug_exception_m <= #1 debug_exception_x; 7.667 + non_debug_exception_m <= #1 non_debug_exception_x; 7.668 `endif 7.669 end 7.670 7.671 @@ -2515,11 +2560,11 @@ 7.672 if (stall_m == `FALSE) 7.673 begin 7.674 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 7.675 - exception_m <= `TRUE; 7.676 + exception_m <= #1 `TRUE; 7.677 else 7.678 - exception_m <= `FALSE; 7.679 + exception_m <= #1 `FALSE; 7.680 `ifdef CFG_BUS_ERRORS_ENABLED 7.681 - data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 7.682 + data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 7.683 `ifdef CFG_DEBUG_ENABLED 7.684 && (reset_exception == `FALSE) 7.685 `endif 7.686 @@ -2529,36 +2574,37 @@ 7.687 7.688 // M/W stage registers 7.689 `ifdef CFG_BUS_ERRORS_ENABLED 7.690 - operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 7.691 + operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 7.692 `else 7.693 - operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 7.694 + operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 7.695 `endif 7.696 - w_result_sel_load_w <= w_result_sel_load_m; 7.697 + w_result_sel_load_w <= #1 w_result_sel_load_m; 7.698 `ifdef CFG_PL_MULTIPLY_ENABLED 7.699 - w_result_sel_mul_w <= w_result_sel_mul_m; 7.700 + w_result_sel_mul_w <= #1 w_result_sel_mul_m; 7.701 `endif 7.702 - write_idx_w <= write_idx_m; 7.703 + write_idx_w <= #1 write_idx_m; 7.704 `ifdef CFG_TRACE_ENABLED 7.705 - eid_w <= eid_m; 7.706 - eret_w <= eret_m; 7.707 + eid_w <= #1 eid_m; 7.708 + eret_w <= #1 eret_m; 7.709 `ifdef CFG_DEBUG_ENABLED 7.710 - bret_w <= bret_m; 7.711 + bret_w <= #1 bret_m; 7.712 `endif 7.713 `endif 7.714 - write_enable_w <= write_enable_m; 7.715 + write_enable_w <= #1 write_enable_m; 7.716 `ifdef CFG_DEBUG_ENABLED 7.717 - debug_exception_w <= debug_exception_m; 7.718 - non_debug_exception_w <= non_debug_exception_m; 7.719 + debug_exception_w <= #1 debug_exception_m; 7.720 + non_debug_exception_w <= #1 non_debug_exception_m; 7.721 `else 7.722 - exception_w <= exception_m; 7.723 + exception_w <= #1 exception_m; 7.724 `endif 7.725 `ifdef CFG_BUS_ERRORS_ENABLED 7.726 if ( (stall_m == `FALSE) 7.727 + && (data_bus_error_exception == `FALSE) 7.728 && ( (load_q_m == `TRUE) 7.729 || (store_q_m == `TRUE) 7.730 ) 7.731 ) 7.732 - memop_pc_w <= pc_m; 7.733 + memop_pc_w <= #1 pc_m; 7.734 `endif 7.735 end 7.736 end 7.737 @@ -2570,26 +2616,26 @@ 7.738 begin 7.739 if (rst_i == `TRUE) 7.740 begin 7.741 - use_buf <= `FALSE; 7.742 - reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 7.743 - reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 7.744 + use_buf <= #1 `FALSE; 7.745 + reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.746 + reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.747 end 7.748 else 7.749 begin 7.750 if (stall_d == `FALSE) 7.751 - use_buf <= `FALSE; 7.752 + use_buf <= #1 `FALSE; 7.753 else if (use_buf == `FALSE) 7.754 begin 7.755 - reg_data_buf_0 <= reg_data_live_0; 7.756 - reg_data_buf_1 <= reg_data_live_1; 7.757 - use_buf <= `TRUE; 7.758 + reg_data_buf_0 <= #1 reg_data_live_0; 7.759 + reg_data_buf_1 <= #1 reg_data_live_1; 7.760 + use_buf <= #1 `TRUE; 7.761 end 7.762 if (reg_write_enable_q_w == `TRUE) 7.763 begin 7.764 if (write_idx_w == read_idx_0_d) 7.765 - reg_data_buf_0 <= w_result; 7.766 + reg_data_buf_0 <= #1 w_result; 7.767 if (write_idx_w == read_idx_1_d) 7.768 - reg_data_buf_1 <= w_result; 7.769 + reg_data_buf_1 <= #1 w_result; 7.770 end 7.771 end 7.772 end 7.773 @@ -2601,42 +2647,42 @@ 7.774 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.775 begin 7.776 if (rst_i == `TRUE) begin 7.777 - registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 7.778 - registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 7.779 - registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 7.780 - registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 7.781 - registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 7.782 - registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 7.783 - registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 7.784 - registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 7.785 - registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 7.786 - registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 7.787 - registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 7.788 - registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 7.789 - registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 7.790 - registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 7.791 - registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 7.792 - registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 7.793 - registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 7.794 - registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 7.795 - registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 7.796 - registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 7.797 - registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 7.798 - registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 7.799 - registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 7.800 - registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 7.801 - registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 7.802 - registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 7.803 - registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 7.804 - registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 7.805 - registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 7.806 - registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 7.807 - registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 7.808 - registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 7.809 + registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.810 + registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.811 + registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.812 + registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.813 + registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.814 + registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.815 + registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.816 + registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.817 + registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.818 + registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.819 + registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.820 + registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.821 + registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.822 + registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.823 + registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.824 + registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.825 + registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.826 + registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.827 + registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.828 + registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.829 + registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.830 + registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.831 + registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.832 + registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.833 + registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.834 + registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.835 + registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.836 + registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.837 + registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.838 + registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.839 + registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.840 + registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.841 end 7.842 else begin 7.843 if (reg_write_enable_q_w == `TRUE) 7.844 - registers[write_idx_w] <= w_result; 7.845 + registers[write_idx_w] <= #1 w_result; 7.846 end 7.847 end 7.848 `endif 7.849 @@ -2647,19 +2693,19 @@ 7.850 begin 7.851 if (rst_i == `TRUE) 7.852 begin 7.853 - trace_pc_valid <= `FALSE; 7.854 - trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 7.855 - trace_exception <= `FALSE; 7.856 - trace_eid <= `LM32_EID_RESET; 7.857 - trace_eret <= `FALSE; 7.858 + trace_pc_valid <= #1 `FALSE; 7.859 + trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 7.860 + trace_exception <= #1 `FALSE; 7.861 + trace_eid <= #1 `LM32_EID_RESET; 7.862 + trace_eret <= #1 `FALSE; 7.863 `ifdef CFG_DEBUG_ENABLED 7.864 - trace_bret <= `FALSE; 7.865 + trace_bret <= #1 `FALSE; 7.866 `endif 7.867 - pc_c <= `CFG_EBA_RESET/4; 7.868 + pc_c <= #1 `CFG_EBA_RESET/4; 7.869 end 7.870 else 7.871 begin 7.872 - trace_pc_valid <= `FALSE; 7.873 + trace_pc_valid <= #1 `FALSE; 7.874 // Has an exception occured 7.875 `ifdef CFG_DEBUG_ENABLED 7.876 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 7.877 @@ -2667,13 +2713,13 @@ 7.878 if (exception_q_w == `TRUE) 7.879 `endif 7.880 begin 7.881 - trace_exception <= `TRUE; 7.882 - trace_pc_valid <= `TRUE; 7.883 - trace_pc <= pc_w; 7.884 - trace_eid <= eid_w; 7.885 + trace_exception <= #1 `TRUE; 7.886 + trace_pc_valid <= #1 `TRUE; 7.887 + trace_pc <= #1 pc_w; 7.888 + trace_eid <= #1 eid_w; 7.889 end 7.890 else 7.891 - trace_exception <= `FALSE; 7.892 + trace_exception <= #1 `FALSE; 7.893 7.894 if ((valid_w == `TRUE) && (!kill_w)) 7.895 begin 7.896 @@ -2681,22 +2727,22 @@ 7.897 if (pc_c + 1'b1 != pc_w) 7.898 begin 7.899 // Non-sequential instruction 7.900 - trace_pc_valid <= `TRUE; 7.901 - trace_pc <= pc_w; 7.902 + trace_pc_valid <= #1 `TRUE; 7.903 + trace_pc <= #1 pc_w; 7.904 end 7.905 // Record PC so we can determine if next instruction is sequential or not 7.906 - pc_c <= pc_w; 7.907 + pc_c <= #1 pc_w; 7.908 // Indicate if it was an eret/bret instruction 7.909 - trace_eret <= eret_w; 7.910 + trace_eret <= #1 eret_w; 7.911 `ifdef CFG_DEBUG_ENABLED 7.912 - trace_bret <= bret_w; 7.913 + trace_bret <= #1 bret_w; 7.914 `endif 7.915 end 7.916 else 7.917 begin 7.918 - trace_eret <= `FALSE; 7.919 + trace_eret <= #1 `FALSE; 7.920 `ifdef CFG_DEBUG_ENABLED 7.921 - trace_bret <= `FALSE; 7.922 + trace_bret <= #1 `FALSE; 7.923 `endif 7.924 end 7.925 end
8.1 --- a/lm32_dcache.v Sun Mar 06 21:14:43 2011 +0000 8.2 +++ b/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 8.3 @@ -1,18 +1,39 @@ 8.4 -// ============================================================================= 8.5 -// COPYRIGHT NOTICE 8.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 8.7 -// ALL RIGHTS RESERVED 8.8 -// This confidential and proprietary software may be used only as authorised by 8.9 -// a licensing agreement from Lattice Semiconductor Corporation. 8.10 -// The entire notice above must be reproduced on all authorized copies and 8.11 -// copies may only be made to the extent permitted by a licensing agreement from 8.12 -// Lattice Semiconductor Corporation. 8.13 +// ================================================================== 8.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 8.15 +// ------------------------------------------------------------------ 8.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 8.17 +// ALL RIGHTS RESERVED 8.18 +// ------------------------------------------------------------------ 8.19 +// 8.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 8.21 +// 8.22 +// Permission: 8.23 +// 8.24 +// Lattice Semiconductor grants permission to use this code 8.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 8.26 +// Open Source License Agreement. 8.27 +// 8.28 +// Disclaimer: 8.29 // 8.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 8.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 8.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 8.33 -// U.S.A email: techsupport@latticesemi.com 8.34 -// =============================================================================/ 8.35 +// Lattice Semiconductor provides no warranty regarding the use or 8.36 +// functionality of this code. It is the user's responsibility to 8.37 +// verify the user’s design for consistency and functionality through 8.38 +// the use of formal verification methods. 8.39 +// 8.40 +// -------------------------------------------------------------------- 8.41 +// 8.42 +// Lattice Semiconductor Corporation 8.43 +// 5555 NE Moore Court 8.44 +// Hillsboro, OR 97214 8.45 +// U.S.A 8.46 +// 8.47 +// TEL: 1-800-Lattice (USA and Canada) 8.48 +// 503-286-8001 (other locations) 8.49 +// 8.50 +// web: http://www.latticesemi.com/ 8.51 +// email: techsupport@latticesemi.com 8.52 +// 8.53 +// -------------------------------------------------------------------- 8.54 // FILE DETAILS 8.55 // Project : LatticeMico32 8.56 // File : lm32_dcache.v 8.57 @@ -420,11 +441,11 @@ 8.58 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.59 begin 8.60 if (rst_i == `TRUE) 8.61 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 8.62 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 8.63 else 8.64 begin 8.65 if (refill_request == `TRUE) 8.66 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 8.67 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 8.68 end 8.69 end 8.70 end 8.71 @@ -434,9 +455,9 @@ 8.72 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.73 begin 8.74 if (rst_i == `TRUE) 8.75 - refilling <= `FALSE; 8.76 + refilling <= #1 `FALSE; 8.77 else 8.78 - refilling <= refill; 8.79 + refilling <= #1 refill; 8.80 end 8.81 8.82 // Instruction cache control FSM 8.83 @@ -444,11 +465,11 @@ 8.84 begin 8.85 if (rst_i == `TRUE) 8.86 begin 8.87 - state <= `LM32_DC_STATE_FLUSH; 8.88 - flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 8.89 - refill_request <= `FALSE; 8.90 - refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 8.91 - restart_request <= `FALSE; 8.92 + state <= #1 `LM32_DC_STATE_FLUSH; 8.93 + flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 8.94 + refill_request <= #1 `FALSE; 8.95 + refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 8.96 + restart_request <= #1 `FALSE; 8.97 end 8.98 else 8.99 begin 8.100 @@ -458,35 +479,35 @@ 8.101 `LM32_DC_STATE_FLUSH: 8.102 begin 8.103 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 8.104 - state <= `LM32_DC_STATE_CHECK; 8.105 - flush_set <= flush_set - 1'b1; 8.106 + state <= #1 `LM32_DC_STATE_CHECK; 8.107 + flush_set <= #1 flush_set - 1'b1; 8.108 end 8.109 8.110 // Check for cache misses 8.111 `LM32_DC_STATE_CHECK: 8.112 begin 8.113 if (stall_a == `FALSE) 8.114 - restart_request <= `FALSE; 8.115 + restart_request <= #1 `FALSE; 8.116 if (miss == `TRUE) 8.117 begin 8.118 - refill_request <= `TRUE; 8.119 - refill_address <= address_m; 8.120 - state <= `LM32_DC_STATE_REFILL; 8.121 + refill_request <= #1 `TRUE; 8.122 + refill_address <= #1 address_m; 8.123 + state <= #1 `LM32_DC_STATE_REFILL; 8.124 end 8.125 else if (dflush == `TRUE) 8.126 - state <= `LM32_DC_STATE_FLUSH; 8.127 + state <= #1 `LM32_DC_STATE_FLUSH; 8.128 end 8.129 8.130 // Refill a cache line 8.131 `LM32_DC_STATE_REFILL: 8.132 begin 8.133 - refill_request <= `FALSE; 8.134 + refill_request <= #1 `FALSE; 8.135 if (refill_ready == `TRUE) 8.136 begin 8.137 if (last_refill == `TRUE) 8.138 begin 8.139 - restart_request <= `TRUE; 8.140 - state <= `LM32_DC_STATE_CHECK; 8.141 + restart_request <= #1 `TRUE; 8.142 + state <= #1 `LM32_DC_STATE_CHECK; 8.143 end 8.144 end 8.145 end 8.146 @@ -502,7 +523,7 @@ 8.147 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.148 begin 8.149 if (rst_i == `TRUE) 8.150 - refill_offset <= {addr_offset_width{1'b0}}; 8.151 + refill_offset <= #1 {addr_offset_width{1'b0}}; 8.152 else 8.153 begin 8.154 case (state) 8.155 @@ -511,14 +532,14 @@ 8.156 `LM32_DC_STATE_CHECK: 8.157 begin 8.158 if (miss == `TRUE) 8.159 - refill_offset <= {addr_offset_width{1'b0}}; 8.160 + refill_offset <= #1 {addr_offset_width{1'b0}}; 8.161 end 8.162 8.163 // Refill a cache line 8.164 `LM32_DC_STATE_REFILL: 8.165 begin 8.166 if (refill_ready == `TRUE) 8.167 - refill_offset <= refill_offset + 1'b1; 8.168 + refill_offset <= #1 refill_offset + 1'b1; 8.169 end 8.170 8.171 endcase
9.1 --- a/lm32_debug.v Sun Mar 06 21:14:43 2011 +0000 9.2 +++ b/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 9.3 @@ -1,18 +1,39 @@ 9.4 -// ============================================================================= 9.5 -// COPYRIGHT NOTICE 9.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 9.7 -// ALL RIGHTS RESERVED 9.8 -// This confidential and proprietary software may be used only as authorised by 9.9 -// a licensing agreement from Lattice Semiconductor Corporation. 9.10 -// The entire notice above must be reproduced on all authorized copies and 9.11 -// copies may only be made to the extent permitted by a licensing agreement from 9.12 -// Lattice Semiconductor Corporation. 9.13 +// ================================================================== 9.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 9.15 +// ------------------------------------------------------------------ 9.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 9.17 +// ALL RIGHTS RESERVED 9.18 +// ------------------------------------------------------------------ 9.19 +// 9.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 9.21 +// 9.22 +// Permission: 9.23 +// 9.24 +// Lattice Semiconductor grants permission to use this code 9.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 9.26 +// Open Source License Agreement. 9.27 +// 9.28 +// Disclaimer: 9.29 // 9.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 9.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 9.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 9.33 -// U.S.A email: techsupport@latticesemi.com 9.34 -// =============================================================================/ 9.35 +// Lattice Semiconductor provides no warranty regarding the use or 9.36 +// functionality of this code. It is the user's responsibility to 9.37 +// verify the user’s design for consistency and functionality through 9.38 +// the use of formal verification methods. 9.39 +// 9.40 +// -------------------------------------------------------------------- 9.41 +// 9.42 +// Lattice Semiconductor Corporation 9.43 +// 5555 NE Moore Court 9.44 +// Hillsboro, OR 97214 9.45 +// U.S.A 9.46 +// 9.47 +// TEL: 1-800-Lattice (USA and Canada) 9.48 +// 503-286-8001 (other locations) 9.49 +// 9.50 +// web: http://www.latticesemi.com/ 9.51 +// email: techsupport@latticesemi.com 9.52 +// 9.53 +// -------------------------------------------------------------------- 9.54 // FILE DETAILS 9.55 // Project : LatticeMico32 9.56 // File : lm32_debug.v 9.57 @@ -226,15 +247,15 @@ 9.58 begin 9.59 if (rst_i == `TRUE) 9.60 begin 9.61 - bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 9.62 - bp_e[i] <= `FALSE; 9.63 + bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 9.64 + bp_e[i] <= #1 `FALSE; 9.65 end 9.66 else 9.67 begin 9.68 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 9.69 begin 9.70 - bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 9.71 - bp_e[i] <= debug_csr_write_data[0]; 9.72 + bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 9.73 + bp_e[i] <= #1 debug_csr_write_data[0]; 9.74 end 9.75 end 9.76 end 9.77 @@ -249,17 +270,17 @@ 9.78 begin 9.79 if (rst_i == `TRUE) 9.80 begin 9.81 - wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 9.82 - wpc_c[i] <= `LM32_WPC_C_DISABLED; 9.83 + wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 9.84 + wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 9.85 end 9.86 else 9.87 begin 9.88 if (debug_csr_write_enable == `TRUE) 9.89 begin 9.90 if (debug_csr == `LM32_CSR_DC) 9.91 - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 9.92 + wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 9.93 if (debug_csr == `LM32_CSR_WP0 + i) 9.94 - wp[i] <= debug_csr_write_data; 9.95 + wp[i] <= #1 debug_csr_write_data; 9.96 end 9.97 end 9.98 end 9.99 @@ -270,11 +291,11 @@ 9.100 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.101 begin 9.102 if (rst_i == `TRUE) 9.103 - dc_re <= `FALSE; 9.104 + dc_re <= #1 `FALSE; 9.105 else 9.106 begin 9.107 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.108 - dc_re <= debug_csr_write_data[1]; 9.109 + dc_re <= #1 debug_csr_write_data[1]; 9.110 end 9.111 end 9.112 9.113 @@ -284,18 +305,18 @@ 9.114 begin 9.115 if (rst_i == `TRUE) 9.116 begin 9.117 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.118 - dc_ss <= `FALSE; 9.119 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.120 + dc_ss <= #1 `FALSE; 9.121 end 9.122 else 9.123 begin 9.124 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.125 begin 9.126 - dc_ss <= debug_csr_write_data[0]; 9.127 + dc_ss <= #1 debug_csr_write_data[0]; 9.128 if (debug_csr_write_data[0] == `FALSE) 9.129 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.130 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.131 else 9.132 - state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 9.133 + state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 9.134 end 9.135 case (state) 9.136 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 9.137 @@ -306,26 +327,26 @@ 9.138 ) 9.139 && (stall_x == `FALSE) 9.140 ) 9.141 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.142 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.143 end 9.144 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 9.145 begin 9.146 // Wait for an instruction to be executed 9.147 if ((q_x == `TRUE) && (stall_x == `FALSE)) 9.148 - state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.149 + state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.150 end 9.151 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 9.152 begin 9.153 // Wait for exception to be raised 9.154 `ifdef CFG_DCACHE_ENABLED 9.155 if (dcache_refill_request == `TRUE) 9.156 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.157 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.158 else 9.159 `endif 9.160 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 9.161 begin 9.162 - dc_ss <= `FALSE; 9.163 - state <= `LM32_DEBUG_SS_STATE_RESTART; 9.164 + dc_ss <= #1 `FALSE; 9.165 + state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 9.166 end 9.167 end 9.168 `LM32_DEBUG_SS_STATE_RESTART: 9.169 @@ -333,10 +354,10 @@ 9.170 // Watch to see if stepped instruction is restarted due to a cache miss 9.171 `ifdef CFG_DCACHE_ENABLED 9.172 if (dcache_refill_request == `TRUE) 9.173 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.174 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.175 else 9.176 `endif 9.177 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.178 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.179 end 9.180 endcase 9.181 end
10.1 --- a/lm32_decoder.v Sun Mar 06 21:14:43 2011 +0000 10.2 +++ b/lm32_decoder.v Sat Aug 06 00:02:46 2011 +0100 10.3 @@ -1,18 +1,39 @@ 10.4 -// ============================================================================= 10.5 -// COPYRIGHT NOTICE 10.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 10.7 -// ALL RIGHTS RESERVED 10.8 -// This confidential and proprietary software may be used only as authorised by 10.9 -// a licensing agreement from Lattice Semiconductor Corporation. 10.10 -// The entire notice above must be reproduced on all authorized copies and 10.11 -// copies may only be made to the extent permitted by a licensing agreement from 10.12 -// Lattice Semiconductor Corporation. 10.13 +// ================================================================== 10.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 10.15 +// ------------------------------------------------------------------ 10.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 10.17 +// ALL RIGHTS RESERVED 10.18 +// ------------------------------------------------------------------ 10.19 +// 10.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 10.21 +// 10.22 +// Permission: 10.23 +// 10.24 +// Lattice Semiconductor grants permission to use this code 10.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 10.26 +// Open Source License Agreement. 10.27 +// 10.28 +// Disclaimer: 10.29 // 10.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 10.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 10.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 10.33 -// U.S.A email: techsupport@latticesemi.com 10.34 -// =============================================================================/ 10.35 +// Lattice Semiconductor provides no warranty regarding the use or 10.36 +// functionality of this code. It is the user's responsibility to 10.37 +// verify the user’s design for consistency and functionality through 10.38 +// the use of formal verification methods. 10.39 +// 10.40 +// -------------------------------------------------------------------- 10.41 +// 10.42 +// Lattice Semiconductor Corporation 10.43 +// 5555 NE Moore Court 10.44 +// Hillsboro, OR 97214 10.45 +// U.S.A 10.46 +// 10.47 +// TEL: 1-800-Lattice (USA and Canada) 10.48 +// 503-286-8001 (other locations) 10.49 +// 10.50 +// web: http://www.latticesemi.com/ 10.51 +// email: techsupport@latticesemi.com 10.52 +// 10.53 +// -------------------------------------------------------------------- 10.54 // FILE DETAILS 10.55 // Project : LatticeMico32 10.56 // File : lm32_decoder.v
11.1 --- a/lm32_functions.v Sun Mar 06 21:14:43 2011 +0000 11.2 +++ b/lm32_functions.v Sat Aug 06 00:02:46 2011 +0100 11.3 @@ -1,18 +1,39 @@ 11.4 -// ============================================================================= 11.5 -// COPYRIGHT NOTICE 11.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 11.7 -// ALL RIGHTS RESERVED 11.8 -// This confidential and proprietary software may be used only as authorised by 11.9 -// a licensing agreement from Lattice Semiconductor Corporation. 11.10 -// The entire notice above must be reproduced on all authorized copies and 11.11 -// copies may only be made to the extent permitted by a licensing agreement from 11.12 -// Lattice Semiconductor Corporation. 11.13 +// ================================================================== 11.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 11.15 +// ------------------------------------------------------------------ 11.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 11.17 +// ALL RIGHTS RESERVED 11.18 +// ------------------------------------------------------------------ 11.19 +// 11.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 11.21 +// 11.22 +// Permission: 11.23 +// 11.24 +// Lattice Semiconductor grants permission to use this code 11.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 11.26 +// Open Source License Agreement. 11.27 +// 11.28 +// Disclaimer: 11.29 // 11.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 11.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 11.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 11.33 -// U.S.A email: techsupport@latticesemi.com 11.34 -// =============================================================================/ 11.35 +// Lattice Semiconductor provides no warranty regarding the use or 11.36 +// functionality of this code. It is the user's responsibility to 11.37 +// verify the user’s design for consistency and functionality through 11.38 +// the use of formal verification methods. 11.39 +// 11.40 +// -------------------------------------------------------------------- 11.41 +// 11.42 +// Lattice Semiconductor Corporation 11.43 +// 5555 NE Moore Court 11.44 +// Hillsboro, OR 97214 11.45 +// U.S.A 11.46 +// 11.47 +// TEL: 1-800-Lattice (USA and Canada) 11.48 +// 503-286-8001 (other locations) 11.49 +// 11.50 +// web: http://www.latticesemi.com/ 11.51 +// email: techsupport@latticesemi.com 11.52 +// 11.53 +// -------------------------------------------------------------------- 11.54 // FILE DETAILS 11.55 // Project : LatticeMico32 11.56 // File : lm32_functions.v
12.1 --- a/lm32_icache.v Sun Mar 06 21:14:43 2011 +0000 12.2 +++ b/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 12.3 @@ -1,18 +1,39 @@ 12.4 -// ============================================================================= 12.5 -// COPYRIGHT NOTICE 12.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 12.7 -// ALL RIGHTS RESERVED 12.8 -// This confidential and proprietary software may be used only as authorised by 12.9 -// a licensing agreement from Lattice Semiconductor Corporation. 12.10 -// The entire notice above must be reproduced on all authorized copies and 12.11 -// copies may only be made to the extent permitted by a licensing agreement from 12.12 -// Lattice Semiconductor Corporation. 12.13 +// ================================================================== 12.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 12.15 +// ------------------------------------------------------------------ 12.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 12.17 +// ALL RIGHTS RESERVED 12.18 +// ------------------------------------------------------------------ 12.19 +// 12.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 12.21 +// 12.22 +// Permission: 12.23 +// 12.24 +// Lattice Semiconductor grants permission to use this code 12.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 12.26 +// Open Source License Agreement. 12.27 +// 12.28 +// Disclaimer: 12.29 // 12.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 12.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 12.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 12.33 -// U.S.A email: techsupport@latticesemi.com 12.34 -// =============================================================================/ 12.35 +// Lattice Semiconductor provides no warranty regarding the use or 12.36 +// functionality of this code. It is the user's responsibility to 12.37 +// verify the user’s design for consistency and functionality through 12.38 +// the use of formal verification methods. 12.39 +// 12.40 +// -------------------------------------------------------------------- 12.41 +// 12.42 +// Lattice Semiconductor Corporation 12.43 +// 5555 NE Moore Court 12.44 +// Hillsboro, OR 97214 12.45 +// U.S.A 12.46 +// 12.47 +// TEL: 1-800-Lattice (USA and Canada) 12.48 +// 503-286-8001 (other locations) 12.49 +// 12.50 +// web: http://www.latticesemi.com/ 12.51 +// email: techsupport@latticesemi.com 12.52 +// 12.53 +// -------------------------------------------------------------------- 12.54 // FILE DETAILS 12.55 // Project : LatticeMico32 12.56 // File : lm32_icache.v 12.57 @@ -359,11 +380,11 @@ 12.58 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.59 begin 12.60 if (rst_i == `TRUE) 12.61 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 12.62 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 12.63 else 12.64 begin 12.65 if (miss == `TRUE) 12.66 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 12.67 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 12.68 end 12.69 end 12.70 end 12.71 @@ -373,9 +394,9 @@ 12.72 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.73 begin 12.74 if (rst_i == `TRUE) 12.75 - refilling <= `FALSE; 12.76 + refilling <= #1 `FALSE; 12.77 else 12.78 - refilling <= refill; 12.79 + refilling <= #1 refill; 12.80 end 12.81 12.82 // Instruction cache control FSM 12.83 @@ -383,10 +404,10 @@ 12.84 begin 12.85 if (rst_i == `TRUE) 12.86 begin 12.87 - state <= `LM32_IC_STATE_FLUSH_INIT; 12.88 - flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 12.89 - refill_address <= {`LM32_PC_WIDTH{1'bx}}; 12.90 - restart_request <= `FALSE; 12.91 + state <= #1 `LM32_IC_STATE_FLUSH_INIT; 12.92 + flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 12.93 + refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 12.94 + restart_request <= #1 `FALSE; 12.95 end 12.96 else 12.97 begin 12.98 @@ -396,8 +417,8 @@ 12.99 `LM32_IC_STATE_FLUSH_INIT: 12.100 begin 12.101 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.102 - state <= `LM32_IC_STATE_CHECK; 12.103 - flush_set <= flush_set - 1'b1; 12.104 + state <= #1 `LM32_IC_STATE_CHECK; 12.105 + flush_set <= #1 flush_set - 1'b1; 12.106 end 12.107 12.108 // Flush the cache in response to an write to the ICC CSR 12.109 @@ -406,28 +427,28 @@ 12.110 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.111 `ifdef CFG_IROM_ENABLED 12.112 if (select_f) 12.113 - state <= `LM32_IC_STATE_REFILL; 12.114 + state <= #1 `LM32_IC_STATE_REFILL; 12.115 else 12.116 `endif 12.117 - state <= `LM32_IC_STATE_CHECK; 12.118 + state <= #1 `LM32_IC_STATE_CHECK; 12.119 12.120 - flush_set <= flush_set - 1'b1; 12.121 + flush_set <= #1 flush_set - 1'b1; 12.122 end 12.123 12.124 // Check for cache misses 12.125 `LM32_IC_STATE_CHECK: 12.126 begin 12.127 if (stall_a == `FALSE) 12.128 - restart_request <= `FALSE; 12.129 + restart_request <= #1 `FALSE; 12.130 if (iflush == `TRUE) 12.131 begin 12.132 - refill_address <= address_f; 12.133 - state <= `LM32_IC_STATE_FLUSH; 12.134 + refill_address <= #1 address_f; 12.135 + state <= #1 `LM32_IC_STATE_FLUSH; 12.136 end 12.137 else if (miss == `TRUE) 12.138 begin 12.139 - refill_address <= address_f; 12.140 - state <= `LM32_IC_STATE_REFILL; 12.141 + refill_address <= #1 address_f; 12.142 + state <= #1 `LM32_IC_STATE_REFILL; 12.143 end 12.144 end 12.145 12.146 @@ -438,8 +459,8 @@ 12.147 begin 12.148 if (last_refill == `TRUE) 12.149 begin 12.150 - restart_request <= `TRUE; 12.151 - state <= `LM32_IC_STATE_CHECK; 12.152 + restart_request <= #1 `TRUE; 12.153 + state <= #1 `LM32_IC_STATE_CHECK; 12.154 end 12.155 end 12.156 end 12.157 @@ -455,7 +476,7 @@ 12.158 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.159 begin 12.160 if (rst_i == `TRUE) 12.161 - refill_offset <= {addr_offset_width{1'b0}}; 12.162 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.163 else 12.164 begin 12.165 case (state) 12.166 @@ -464,16 +485,16 @@ 12.167 `LM32_IC_STATE_CHECK: 12.168 begin 12.169 if (iflush == `TRUE) 12.170 - refill_offset <= {addr_offset_width{1'b0}}; 12.171 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.172 else if (miss == `TRUE) 12.173 - refill_offset <= {addr_offset_width{1'b0}}; 12.174 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.175 end 12.176 12.177 // Refill a cache line 12.178 `LM32_IC_STATE_REFILL: 12.179 begin 12.180 if (refill_ready == `TRUE) 12.181 - refill_offset <= refill_offset + 1'b1; 12.182 + refill_offset <= #1 refill_offset + 1'b1; 12.183 end 12.184 12.185 endcase
13.1 --- a/lm32_include.v Sun Mar 06 21:14:43 2011 +0000 13.2 +++ b/lm32_include.v Sat Aug 06 00:02:46 2011 +0100 13.3 @@ -1,18 +1,39 @@ 13.4 -// ============================================================================= 13.5 -// COPYRIGHT NOTICE 13.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 13.7 -// ALL RIGHTS RESERVED 13.8 -// This confidential and proprietary software may be used only as authorised by 13.9 -// a licensing agreement from Lattice Semiconductor Corporation. 13.10 -// The entire notice above must be reproduced on all authorized copies and 13.11 -// copies may only be made to the extent permitted by a licensing agreement from 13.12 -// Lattice Semiconductor Corporation. 13.13 +// ================================================================== 13.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 13.15 +// ------------------------------------------------------------------ 13.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 13.17 +// ALL RIGHTS RESERVED 13.18 +// ------------------------------------------------------------------ 13.19 +// 13.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 13.21 +// 13.22 +// Permission: 13.23 +// 13.24 +// Lattice Semiconductor grants permission to use this code 13.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 13.26 +// Open Source License Agreement. 13.27 +// 13.28 +// Disclaimer: 13.29 // 13.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 13.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 13.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 13.33 -// U.S.A email: techsupport@latticesemi.com 13.34 -// =============================================================================/ 13.35 +// Lattice Semiconductor provides no warranty regarding the use or 13.36 +// functionality of this code. It is the user's responsibility to 13.37 +// verify the user’s design for consistency and functionality through 13.38 +// the use of formal verification methods. 13.39 +// 13.40 +// -------------------------------------------------------------------- 13.41 +// 13.42 +// Lattice Semiconductor Corporation 13.43 +// 5555 NE Moore Court 13.44 +// Hillsboro, OR 97214 13.45 +// U.S.A 13.46 +// 13.47 +// TEL: 1-800-Lattice (USA and Canada) 13.48 +// 503-286-8001 (other locations) 13.49 +// 13.50 +// web: http://www.latticesemi.com/ 13.51 +// email: techsupport@latticesemi.com 13.52 +// 13.53 +// -------------------------------------------------------------------- 13.54 // FILE DETAILS 13.55 // Project : LatticeMico32 13.56 // File : lm32_include.v
14.1 --- a/lm32_instruction_unit.v Sun Mar 06 21:14:43 2011 +0000 14.2 +++ b/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 14.3 @@ -1,18 +1,39 @@ 14.4 -// ============================================================================= 14.5 -// COPYRIGHT NOTICE 14.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 14.7 -// ALL RIGHTS RESERVED 14.8 -// This confidential and proprietary software may be used only as authorised by 14.9 -// a licensing agreement from Lattice Semiconductor Corporation. 14.10 -// The entire notice above must be reproduced on all authorized copies and 14.11 -// copies may only be made to the extent permitted by a licensing agreement from 14.12 -// Lattice Semiconductor Corporation. 14.13 +// ================================================================== 14.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 14.15 +// ------------------------------------------------------------------ 14.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 14.17 +// ALL RIGHTS RESERVED 14.18 +// ------------------------------------------------------------------ 14.19 +// 14.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 14.21 +// 14.22 +// Permission: 14.23 +// 14.24 +// Lattice Semiconductor grants permission to use this code 14.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 14.26 +// Open Source License Agreement. 14.27 +// 14.28 +// Disclaimer: 14.29 // 14.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 14.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 14.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 14.33 -// U.S.A email: techsupport@latticesemi.com 14.34 -// =============================================================================/ 14.35 +// Lattice Semiconductor provides no warranty regarding the use or 14.36 +// functionality of this code. It is the user's responsibility to 14.37 +// verify the user’s design for consistency and functionality through 14.38 +// the use of formal verification methods. 14.39 +// 14.40 +// -------------------------------------------------------------------- 14.41 +// 14.42 +// Lattice Semiconductor Corporation 14.43 +// 5555 NE Moore Court 14.44 +// Hillsboro, OR 97214 14.45 +// U.S.A 14.46 +// 14.47 +// TEL: 1-800-Lattice (USA and Canada) 14.48 +// 503-286-8001 (other locations) 14.49 +// 14.50 +// web: http://www.latticesemi.com/ 14.51 +// email: techsupport@latticesemi.com 14.52 +// 14.53 +// -------------------------------------------------------------------- 14.54 // FILE DETAILS 14.55 // Project : LatticeMico32 14.56 // File : lm32_instruction_unit.v 14.57 @@ -42,6 +63,9 @@ 14.58 // : instruction cache) to lock up in to an infinite loop due to a 14.59 // : instruction bus error when EBA was set to instruction inline 14.60 // : memory. 14.61 +// Version : 3.8 14.62 +// : Feature: Support for dynamically switching EBA to DEBA via a 14.63 +// : GPIO. 14.64 // ============================================================================= 14.65 14.66 `include "lm32_include.v" 14.67 @@ -54,6 +78,11 @@ 14.68 // ----- Inputs ------- 14.69 clk_i, 14.70 rst_i, 14.71 +`ifdef CFG_DEBUG_ENABLED 14.72 + `ifdef CFG_ALTERNATE_EBA 14.73 + at_debug, 14.74 + `endif 14.75 +`endif 14.76 // From pipeline 14.77 stall_a, 14.78 stall_f, 14.79 @@ -161,6 +190,12 @@ 14.80 input clk_i; // Clock 14.81 input rst_i; // Reset 14.82 14.83 +`ifdef CFG_DEBUG_ENABLED 14.84 + `ifdef CFG_ALTERNATE_EBA 14.85 + input at_debug; // GPIO input that maps EBA to DEBA 14.86 + `endif 14.87 +`endif 14.88 + 14.89 input stall_a; // Stall A stage instruction 14.90 input stall_f; // Stall F stage instruction 14.91 input stall_d; // Stall D stage instruction 14.92 @@ -334,6 +369,10 @@ 14.93 reg jtag_access; // Indicates if a JTAG WB access is in progress 14.94 `endif 14.95 14.96 +`ifdef CFG_ALTERNATE_EBA 14.97 + reg alternate_eba_taken; 14.98 +`endif 14.99 + 14.100 ///////////////////////////////////////////////////// 14.101 // Functions 14.102 ///////////////////////////////////////////////////// 14.103 @@ -381,8 +420,8 @@ 14.104 .ResetB (rst_i), 14.105 .DataInA ({32{1'b0}}), 14.106 .DataInB (irom_store_data_m), 14.107 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.108 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.109 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 14.110 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 14.111 .ClockEnA (!stall_a), 14.112 .ClockEnB (!stall_x || !stall_m), 14.113 .WrA (`FALSE), 14.114 @@ -469,7 +508,7 @@ 14.115 pc_a = restart_address; 14.116 else 14.117 `endif 14.118 - pc_a = pc_f + 1'b1; 14.119 + pc_a = pc_f + 1'b1; 14.120 end 14.121 14.122 // Select where instruction should be fetched from 14.123 @@ -542,52 +581,63 @@ 14.124 14.125 // PC 14.126 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.127 -begin 14.128 - if (rst_i == `TRUE) 14.129 - begin 14.130 - pc_f <= (`CFG_EBA_RESET-4)/4; 14.131 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 14.132 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 14.133 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 14.134 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 14.135 - end 14.136 - else 14.137 - begin 14.138 - if (stall_f == `FALSE) 14.139 - pc_f <= pc_a; 14.140 - if (stall_d == `FALSE) 14.141 - pc_d <= pc_f; 14.142 - if (stall_x == `FALSE) 14.143 - pc_x <= pc_d; 14.144 - if (stall_m == `FALSE) 14.145 - pc_m <= pc_x; 14.146 - pc_w <= pc_m; 14.147 - end 14.148 -end 14.149 + begin 14.150 + if (rst_i == `TRUE) 14.151 + begin 14.152 +`ifdef CFG_DEBUG_ENABLED 14.153 + `ifdef CFG_ALTERNATE_EBA 14.154 + if (at_debug == `TRUE) 14.155 + pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 14.156 + else 14.157 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.158 + `else 14.159 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.160 + `endif 14.161 +`else 14.162 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.163 +`endif 14.164 + pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.165 + pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.166 + pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.167 + pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.168 + end 14.169 + else 14.170 + begin 14.171 + if (stall_f == `FALSE) 14.172 + pc_f <= #1 pc_a; 14.173 + if (stall_d == `FALSE) 14.174 + pc_d <= #1 pc_f; 14.175 + if (stall_x == `FALSE) 14.176 + pc_x <= #1 pc_d; 14.177 + if (stall_m == `FALSE) 14.178 + pc_m <= #1 pc_x; 14.179 + pc_w <= #1 pc_m; 14.180 + end 14.181 + end 14.182 14.183 `ifdef LM32_CACHE_ENABLED 14.184 // Address to restart from after a cache miss has been handled 14.185 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.186 begin 14.187 if (rst_i == `TRUE) 14.188 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 14.189 + restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.190 else 14.191 begin 14.192 `ifdef CFG_DCACHE_ENABLED 14.193 `ifdef CFG_ICACHE_ENABLED 14.194 // D-cache restart address must take priority, otherwise instructions will be lost 14.195 if (dcache_refill_request == `TRUE) 14.196 - restart_address <= pc_w; 14.197 + restart_address <= #1 pc_w; 14.198 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 14.199 - restart_address <= icache_refill_address; 14.200 + restart_address <= #1 icache_refill_address; 14.201 `else 14.202 if (dcache_refill_request == `TRUE) 14.203 - restart_address <= pc_w; 14.204 + restart_address <= #1 pc_w; 14.205 `endif 14.206 `else 14.207 `ifdef CFG_ICACHE_ENABLED 14.208 if (icache_refill_request == `TRUE) 14.209 - restart_address <= icache_refill_address; 14.210 + restart_address <= #1 icache_refill_address; 14.211 `endif 14.212 `endif 14.213 end 14.214 @@ -599,11 +649,11 @@ 14.215 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.216 begin 14.217 if (rst_i == `TRUE) 14.218 - irom_select_f <= `FALSE; 14.219 + irom_select_f <= #1 `FALSE; 14.220 else 14.221 begin 14.222 if (stall_f == `FALSE) 14.223 - irom_select_f <= irom_select_a; 14.224 + irom_select_f <= #1 irom_select_a; 14.225 end 14.226 end 14.227 `endif 14.228 @@ -628,25 +678,25 @@ 14.229 begin 14.230 if (rst_i == `TRUE) 14.231 begin 14.232 - i_cyc_o <= `FALSE; 14.233 - i_stb_o <= `FALSE; 14.234 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.235 - i_cti_o <= `LM32_CTYPE_END; 14.236 - i_lock_o <= `FALSE; 14.237 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.238 - icache_refill_ready <= `FALSE; 14.239 + i_cyc_o <= #1 `FALSE; 14.240 + i_stb_o <= #1 `FALSE; 14.241 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 14.242 + i_cti_o <= #1 `LM32_CTYPE_END; 14.243 + i_lock_o <= #1 `FALSE; 14.244 + icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.245 + icache_refill_ready <= #1 `FALSE; 14.246 `ifdef CFG_BUS_ERRORS_ENABLED 14.247 - bus_error_f <= `FALSE; 14.248 + bus_error_f <= #1 `FALSE; 14.249 `endif 14.250 `ifdef CFG_HW_DEBUG_ENABLED 14.251 - i_we_o <= `FALSE; 14.252 - i_sel_o <= 4'b1111; 14.253 - jtag_access <= `FALSE; 14.254 + i_we_o <= #1 `FALSE; 14.255 + i_sel_o <= #1 4'b1111; 14.256 + jtag_access <= #1 `FALSE; 14.257 `endif 14.258 end 14.259 else 14.260 begin 14.261 - icache_refill_ready <= `FALSE; 14.262 + icache_refill_ready <= #1 `FALSE; 14.263 // Is a cycle in progress? 14.264 if (i_cyc_o == `TRUE) 14.265 begin 14.266 @@ -656,10 +706,10 @@ 14.267 `ifdef CFG_HW_DEBUG_ENABLED 14.268 if (jtag_access == `TRUE) 14.269 begin 14.270 - i_cyc_o <= `FALSE; 14.271 - i_stb_o <= `FALSE; 14.272 - i_we_o <= `FALSE; 14.273 - jtag_access <= `FALSE; 14.274 + i_cyc_o <= #1 `FALSE; 14.275 + i_stb_o <= #1 `FALSE; 14.276 + i_we_o <= #1 `FALSE; 14.277 + jtag_access <= #1 `FALSE; 14.278 end 14.279 else 14.280 `endif 14.281 @@ -667,22 +717,22 @@ 14.282 if (last_word == `TRUE) 14.283 begin 14.284 // Cache line fill complete 14.285 - i_cyc_o <= `FALSE; 14.286 - i_stb_o <= `FALSE; 14.287 - i_lock_o <= `FALSE; 14.288 + i_cyc_o <= #1 `FALSE; 14.289 + i_stb_o <= #1 `FALSE; 14.290 + i_lock_o <= #1 `FALSE; 14.291 end 14.292 // Fetch next word in cache line 14.293 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 14.294 - i_cti_o <= next_cycle_type; 14.295 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 14.296 + i_cti_o <= #1 next_cycle_type; 14.297 // Write fetched data into instruction cache 14.298 - icache_refill_ready <= `TRUE; 14.299 - icache_refill_data <= i_dat_i; 14.300 + icache_refill_ready <= #1 `TRUE; 14.301 + icache_refill_data <= #1 i_dat_i; 14.302 end 14.303 end 14.304 `ifdef CFG_BUS_ERRORS_ENABLED 14.305 if (i_err_i == `TRUE) 14.306 begin 14.307 - bus_error_f <= `TRUE; 14.308 + bus_error_f <= #1 `TRUE; 14.309 $display ("Instruction bus error. Address: %x", i_adr_o); 14.310 end 14.311 `endif 14.312 @@ -693,15 +743,15 @@ 14.313 begin 14.314 // Read first word of cache line 14.315 `ifdef CFG_HW_DEBUG_ENABLED 14.316 - i_sel_o <= 4'b1111; 14.317 + i_sel_o <= #1 4'b1111; 14.318 `endif 14.319 - i_adr_o <= {first_address, 2'b00}; 14.320 - i_cyc_o <= `TRUE; 14.321 - i_stb_o <= `TRUE; 14.322 - i_cti_o <= first_cycle_type; 14.323 - //i_lock_o <= `TRUE; 14.324 + i_adr_o <= #1 {first_address, 2'b00}; 14.325 + i_cyc_o <= #1 `TRUE; 14.326 + i_stb_o <= #1 `TRUE; 14.327 + i_cti_o <= #1 first_cycle_type; 14.328 + //i_lock_o <= #1 `TRUE; 14.329 `ifdef CFG_BUS_ERRORS_ENABLED 14.330 - bus_error_f <= `FALSE; 14.331 + bus_error_f <= #1 `FALSE; 14.332 `endif 14.333 end 14.334 `ifdef CFG_HW_DEBUG_ENABLED 14.335 @@ -710,18 +760,18 @@ 14.336 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 14.337 begin 14.338 case (jtag_address[1:0]) 14.339 - 2'b00: i_sel_o <= 4'b1000; 14.340 - 2'b01: i_sel_o <= 4'b0100; 14.341 - 2'b10: i_sel_o <= 4'b0010; 14.342 - 2'b11: i_sel_o <= 4'b0001; 14.343 + 2'b00: i_sel_o <= #1 4'b1000; 14.344 + 2'b01: i_sel_o <= #1 4'b0100; 14.345 + 2'b10: i_sel_o <= #1 4'b0010; 14.346 + 2'b11: i_sel_o <= #1 4'b0001; 14.347 endcase 14.348 - i_adr_o <= jtag_address; 14.349 - i_dat_o <= {4{jtag_write_data}}; 14.350 - i_cyc_o <= `TRUE; 14.351 - i_stb_o <= `TRUE; 14.352 - i_we_o <= jtag_write_enable; 14.353 - i_cti_o <= `LM32_CTYPE_END; 14.354 - jtag_access <= `TRUE; 14.355 + i_adr_o <= #1 jtag_address; 14.356 + i_dat_o <= #1 {4{jtag_write_data}}; 14.357 + i_cyc_o <= #1 `TRUE; 14.358 + i_stb_o <= #1 `TRUE; 14.359 + i_we_o <= #1 jtag_write_enable; 14.360 + i_cti_o <= #1 `LM32_CTYPE_END; 14.361 + jtag_access <= #1 `TRUE; 14.362 end 14.363 end 14.364 `endif 14.365 @@ -730,10 +780,10 @@ 14.366 // continually generated if exception handler is cached 14.367 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.368 if (branch_taken_x == `TRUE) 14.369 - bus_error_f <= `FALSE; 14.370 + bus_error_f <= #1 `FALSE; 14.371 `endif 14.372 if (branch_taken_m == `TRUE) 14.373 - bus_error_f <= `FALSE; 14.374 + bus_error_f <= #1 `FALSE; 14.375 `endif 14.376 end 14.377 end 14.378 @@ -743,14 +793,14 @@ 14.379 begin 14.380 if (rst_i == `TRUE) 14.381 begin 14.382 - i_cyc_o <= `FALSE; 14.383 - i_stb_o <= `FALSE; 14.384 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.385 - i_cti_o <= `LM32_CTYPE_END; 14.386 - i_lock_o <= `FALSE; 14.387 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.388 + i_cyc_o <= #1 `FALSE; 14.389 + i_stb_o <= #1 `FALSE; 14.390 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 14.391 + i_cti_o <= #1 `LM32_CTYPE_END; 14.392 + i_lock_o <= #1 `FALSE; 14.393 + wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.394 `ifdef CFG_BUS_ERRORS_ENABLED 14.395 - bus_error_f <= `FALSE; 14.396 + bus_error_f <= #1 `FALSE; 14.397 `endif 14.398 end 14.399 else 14.400 @@ -762,15 +812,15 @@ 14.401 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 14.402 begin 14.403 // Cycle complete 14.404 - i_cyc_o <= `FALSE; 14.405 - i_stb_o <= `FALSE; 14.406 + i_cyc_o <= #1 `FALSE; 14.407 + i_stb_o <= #1 `FALSE; 14.408 // Register fetched instruction 14.409 - wb_data_f <= i_dat_i; 14.410 + wb_data_f <= #1 i_dat_i; 14.411 end 14.412 `ifdef CFG_BUS_ERRORS_ENABLED 14.413 if (i_err_i == `TRUE) 14.414 begin 14.415 - bus_error_f <= `TRUE; 14.416 + bus_error_f <= #1 `TRUE; 14.417 $display ("Instruction bus error. Address: %x", i_adr_o); 14.418 end 14.419 `endif 14.420 @@ -786,13 +836,13 @@ 14.421 begin 14.422 // Fetch instruction 14.423 `ifdef CFG_HW_DEBUG_ENABLED 14.424 - i_sel_o <= 4'b1111; 14.425 + i_sel_o <= #1 4'b1111; 14.426 `endif 14.427 - i_adr_o <= {pc_a, 2'b00}; 14.428 - i_cyc_o <= `TRUE; 14.429 - i_stb_o <= `TRUE; 14.430 + i_adr_o <= #1 {pc_a, 2'b00}; 14.431 + i_cyc_o <= #1 `TRUE; 14.432 + i_stb_o <= #1 `TRUE; 14.433 `ifdef CFG_BUS_ERRORS_ENABLED 14.434 - bus_error_f <= `FALSE; 14.435 + bus_error_f <= #1 `FALSE; 14.436 `endif 14.437 end 14.438 else 14.439 @@ -804,7 +854,7 @@ 14.440 ) 14.441 begin 14.442 `ifdef CFG_BUS_ERRORS_ENABLED 14.443 - bus_error_f <= `FALSE; 14.444 + bus_error_f <= #1 `FALSE; 14.445 `endif 14.446 end 14.447 end 14.448 @@ -819,18 +869,18 @@ 14.449 begin 14.450 if (rst_i == `TRUE) 14.451 begin 14.452 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.453 + instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.454 `ifdef CFG_BUS_ERRORS_ENABLED 14.455 - bus_error_d <= `FALSE; 14.456 + bus_error_d <= #1 `FALSE; 14.457 `endif 14.458 end 14.459 else 14.460 begin 14.461 if (stall_d == `FALSE) 14.462 begin 14.463 - instruction_d <= instruction_f; 14.464 + instruction_d <= #1 instruction_f; 14.465 `ifdef CFG_BUS_ERRORS_ENABLED 14.466 - bus_error_d <= bus_error_f; 14.467 + bus_error_d <= #1 bus_error_f; 14.468 `endif 14.469 end 14.470 end
15.1 --- a/lm32_interrupt.v Sun Mar 06 21:14:43 2011 +0000 15.2 +++ b/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 15.3 @@ -1,18 +1,39 @@ 15.4 -// ============================================================================= 15.5 -// COPYRIGHT NOTICE 15.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 15.7 -// ALL RIGHTS RESERVED 15.8 -// This confidential and proprietary software may be used only as authorised by 15.9 -// a licensing agreement from Lattice Semiconductor Corporation. 15.10 -// The entire notice above must be reproduced on all authorized copies and 15.11 -// copies may only be made to the extent permitted by a licensing agreement from 15.12 -// Lattice Semiconductor Corporation. 15.13 +// ================================================================== 15.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 15.15 +// ------------------------------------------------------------------ 15.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 15.17 +// ALL RIGHTS RESERVED 15.18 +// ------------------------------------------------------------------ 15.19 +// 15.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 15.21 +// 15.22 +// Permission: 15.23 +// 15.24 +// Lattice Semiconductor grants permission to use this code 15.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 15.26 +// Open Source License Agreement. 15.27 +// 15.28 +// Disclaimer: 15.29 // 15.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 15.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 15.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 15.33 -// U.S.A email: techsupport@latticesemi.com 15.34 -// =============================================================================/ 15.35 +// Lattice Semiconductor provides no warranty regarding the use or 15.36 +// functionality of this code. It is the user's responsibility to 15.37 +// verify the user’s design for consistency and functionality through 15.38 +// the use of formal verification methods. 15.39 +// 15.40 +// -------------------------------------------------------------------- 15.41 +// 15.42 +// Lattice Semiconductor Corporation 15.43 +// 5555 NE Moore Court 15.44 +// Hillsboro, OR 97214 15.45 +// U.S.A 15.46 +// 15.47 +// TEL: 1-800-Lattice (USA and Canada) 15.48 +// 503-286-8001 (other locations) 15.49 +// 15.50 +// web: http://www.latticesemi.com/ 15.51 +// email: techsupport@latticesemi.com 15.52 +// 15.53 +// -------------------------------------------------------------------- 15.54 // FILE DETAILS 15.55 // Project : LatticeMico32 15.56 // File : lm32_interrupt.v 15.57 @@ -199,64 +220,64 @@ 15.58 begin 15.59 if (rst_i == `TRUE) 15.60 begin 15.61 - ie <= `FALSE; 15.62 - eie <= `FALSE; 15.63 + ie <= #1 `FALSE; 15.64 + eie <= #1 `FALSE; 15.65 `ifdef CFG_DEBUG_ENABLED 15.66 - bie <= `FALSE; 15.67 + bie <= #1 `FALSE; 15.68 `endif 15.69 - im <= {interrupts{1'b0}}; 15.70 - ip <= {interrupts{1'b0}}; 15.71 + im <= #1 {interrupts{1'b0}}; 15.72 + ip <= #1 {interrupts{1'b0}}; 15.73 end 15.74 else 15.75 begin 15.76 // Set IP bit when interrupt line is asserted 15.77 - ip <= asserted; 15.78 + ip <= #1 asserted; 15.79 `ifdef CFG_DEBUG_ENABLED 15.80 if (non_debug_exception == `TRUE) 15.81 begin 15.82 // Save and then clear interrupt enable 15.83 - eie <= ie; 15.84 - ie <= `FALSE; 15.85 + eie <= #1 ie; 15.86 + ie <= #1 `FALSE; 15.87 end 15.88 else if (debug_exception == `TRUE) 15.89 begin 15.90 // Save and then clear interrupt enable 15.91 - bie <= ie; 15.92 - ie <= `FALSE; 15.93 + bie <= #1 ie; 15.94 + ie <= #1 `FALSE; 15.95 end 15.96 `else 15.97 if (exception == `TRUE) 15.98 begin 15.99 // Save and then clear interrupt enable 15.100 - eie <= ie; 15.101 - ie <= `FALSE; 15.102 + eie <= #1 ie; 15.103 + ie <= #1 `FALSE; 15.104 end 15.105 `endif 15.106 else if (stall_x == `FALSE) 15.107 begin 15.108 if (eret_q_x == `TRUE) 15.109 // Restore interrupt enable 15.110 - ie <= eie; 15.111 + ie <= #1 eie; 15.112 `ifdef CFG_DEBUG_ENABLED 15.113 else if (bret_q_x == `TRUE) 15.114 // Restore interrupt enable 15.115 - ie <= bie; 15.116 + ie <= #1 bie; 15.117 `endif 15.118 else if (csr_write_enable == `TRUE) 15.119 begin 15.120 // Handle wcsr write 15.121 if (csr == `LM32_CSR_IE) 15.122 begin 15.123 - ie <= csr_write_data[0]; 15.124 - eie <= csr_write_data[1]; 15.125 + ie <= #1 csr_write_data[0]; 15.126 + eie <= #1 csr_write_data[1]; 15.127 `ifdef CFG_DEBUG_ENABLED 15.128 - bie <= csr_write_data[2]; 15.129 + bie <= #1 csr_write_data[2]; 15.130 `endif 15.131 end 15.132 if (csr == `LM32_CSR_IM) 15.133 - im <= csr_write_data[interrupts-1:0]; 15.134 + im <= #1 csr_write_data[interrupts-1:0]; 15.135 if (csr == `LM32_CSR_IP) 15.136 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.137 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 15.138 end 15.139 end 15.140 end 15.141 @@ -269,61 +290,61 @@ 15.142 begin 15.143 if (rst_i == `TRUE) 15.144 begin 15.145 - ie <= `FALSE; 15.146 - eie <= `FALSE; 15.147 + ie <= #1 `FALSE; 15.148 + eie <= #1 `FALSE; 15.149 `ifdef CFG_DEBUG_ENABLED 15.150 - bie <= `FALSE; 15.151 + bie <= #1 `FALSE; 15.152 `endif 15.153 - ip <= {interrupts{1'b0}}; 15.154 + ip <= #1 {interrupts{1'b0}}; 15.155 end 15.156 else 15.157 begin 15.158 // Set IP bit when interrupt line is asserted 15.159 - ip <= asserted; 15.160 + ip <= #1 asserted; 15.161 `ifdef CFG_DEBUG_ENABLED 15.162 if (non_debug_exception == `TRUE) 15.163 begin 15.164 // Save and then clear interrupt enable 15.165 - eie <= ie; 15.166 - ie <= `FALSE; 15.167 + eie <= #1 ie; 15.168 + ie <= #1 `FALSE; 15.169 end 15.170 else if (debug_exception == `TRUE) 15.171 begin 15.172 // Save and then clear interrupt enable 15.173 - bie <= ie; 15.174 - ie <= `FALSE; 15.175 + bie <= #1 ie; 15.176 + ie <= #1 `FALSE; 15.177 end 15.178 `else 15.179 if (exception == `TRUE) 15.180 begin 15.181 // Save and then clear interrupt enable 15.182 - eie <= ie; 15.183 - ie <= `FALSE; 15.184 + eie <= #1 ie; 15.185 + ie <= #1 `FALSE; 15.186 end 15.187 `endif 15.188 else if (stall_x == `FALSE) 15.189 begin 15.190 if (eret_q_x == `TRUE) 15.191 // Restore interrupt enable 15.192 - ie <= eie; 15.193 + ie <= #1 eie; 15.194 `ifdef CFG_DEBUG_ENABLED 15.195 else if (bret_q_x == `TRUE) 15.196 // Restore interrupt enable 15.197 - ie <= bie; 15.198 + ie <= #1 bie; 15.199 `endif 15.200 else if (csr_write_enable == `TRUE) 15.201 begin 15.202 // Handle wcsr write 15.203 if (csr == `LM32_CSR_IE) 15.204 begin 15.205 - ie <= csr_write_data[0]; 15.206 - eie <= csr_write_data[1]; 15.207 + ie <= #1 csr_write_data[0]; 15.208 + eie <= #1 csr_write_data[1]; 15.209 `ifdef CFG_DEBUG_ENABLED 15.210 - bie <= csr_write_data[2]; 15.211 + bie <= #1 csr_write_data[2]; 15.212 `endif 15.213 end 15.214 if (csr == `LM32_CSR_IP) 15.215 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.216 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 15.217 end 15.218 end 15.219 end
16.1 --- a/lm32_jtag.v Sun Mar 06 21:14:43 2011 +0000 16.2 +++ b/lm32_jtag.v Sat Aug 06 00:02:46 2011 +0100 16.3 @@ -1,18 +1,39 @@ 16.4 -// ============================================================================= 16.5 -// COPYRIGHT NOTICE 16.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 16.7 -// ALL RIGHTS RESERVED 16.8 -// This confidential and proprietary software may be used only as authorised by 16.9 -// a licensing agreement from Lattice Semiconductor Corporation. 16.10 -// The entire notice above must be reproduced on all authorized copies and 16.11 -// copies may only be made to the extent permitted by a licensing agreement from 16.12 -// Lattice Semiconductor Corporation. 16.13 +// ================================================================== 16.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 16.15 +// ------------------------------------------------------------------ 16.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 16.17 +// ALL RIGHTS RESERVED 16.18 +// ------------------------------------------------------------------ 16.19 +// 16.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 16.21 +// 16.22 +// Permission: 16.23 +// 16.24 +// Lattice Semiconductor grants permission to use this code 16.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 16.26 +// Open Source License Agreement. 16.27 +// 16.28 +// Disclaimer: 16.29 // 16.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 16.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 16.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 16.33 -// U.S.A email: techsupport@latticesemi.com 16.34 -// =============================================================================/ 16.35 +// Lattice Semiconductor provides no warranty regarding the use or 16.36 +// functionality of this code. It is the user's responsibility to 16.37 +// verify the user’s design for consistency and functionality through 16.38 +// the use of formal verification methods. 16.39 +// 16.40 +// -------------------------------------------------------------------- 16.41 +// 16.42 +// Lattice Semiconductor Corporation 16.43 +// 5555 NE Moore Court 16.44 +// Hillsboro, OR 97214 16.45 +// U.S.A 16.46 +// 16.47 +// TEL: 1-800-Lattice (USA and Canada) 16.48 +// 503-286-8001 (other locations) 16.49 +// 16.50 +// web: http://www.latticesemi.com/ 16.51 +// email: techsupport@latticesemi.com 16.52 +// 16.53 +// -------------------------------------------------------------------- 16.54 // FILE DETAILS 16.55 // Project : LatticeMico32 16.56 // File : lm32_jtag.v 16.57 @@ -236,9 +257,9 @@ 16.58 always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 16.59 begin 16.60 if (rst_i == `TRUE) 16.61 - rx_toggle <= 1'b0; 16.62 + rx_toggle <= #1 1'b0; 16.63 else 16.64 - rx_toggle <= ~rx_toggle; 16.65 + rx_toggle <= #1 ~rx_toggle; 16.66 end 16.67 16.68 always @(*) 16.69 @@ -252,15 +273,15 @@ 16.70 begin 16.71 if (rst_i == `TRUE) 16.72 begin 16.73 - rx_toggle_r <= 1'b0; 16.74 - rx_toggle_r_r <= 1'b0; 16.75 - rx_toggle_r_r_r <= 1'b0; 16.76 + rx_toggle_r <= #1 1'b0; 16.77 + rx_toggle_r_r <= #1 1'b0; 16.78 + rx_toggle_r_r_r <= #1 1'b0; 16.79 end 16.80 else 16.81 begin 16.82 - rx_toggle_r <= rx_toggle; 16.83 - rx_toggle_r_r <= rx_toggle_r; 16.84 - rx_toggle_r_r_r <= rx_toggle_r_r; 16.85 + rx_toggle_r <= #1 rx_toggle; 16.86 + rx_toggle_r_r <= #1 rx_toggle_r; 16.87 + rx_toggle_r_r_r <= #1 rx_toggle_r_r; 16.88 end 16.89 end 16.90 16.91 @@ -269,24 +290,24 @@ 16.92 begin 16.93 if (rst_i == `TRUE) 16.94 begin 16.95 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.96 - command <= 4'b0000; 16.97 - jtag_reg_d <= 8'h00; 16.98 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.99 + command <= #1 4'b0000; 16.100 + jtag_reg_d <= #1 8'h00; 16.101 `ifdef CFG_HW_DEBUG_ENABLED 16.102 - processing <= `FALSE; 16.103 - jtag_csr_write_enable <= `FALSE; 16.104 - jtag_read_enable <= `FALSE; 16.105 - jtag_write_enable <= `FALSE; 16.106 + processing <= #1 `FALSE; 16.107 + jtag_csr_write_enable <= #1 `FALSE; 16.108 + jtag_read_enable <= #1 `FALSE; 16.109 + jtag_write_enable <= #1 `FALSE; 16.110 `endif 16.111 `ifdef CFG_DEBUG_ENABLED 16.112 - jtag_break <= `FALSE; 16.113 - jtag_reset <= `FALSE; 16.114 + jtag_break <= #1 `FALSE; 16.115 + jtag_reset <= #1 `FALSE; 16.116 `endif 16.117 `ifdef CFG_JTAG_UART_ENABLED 16.118 - uart_tx_byte <= 8'h00; 16.119 - uart_tx_valid <= `FALSE; 16.120 - uart_rx_byte <= 8'h00; 16.121 - uart_rx_valid <= `FALSE; 16.122 + uart_tx_byte <= #1 8'h00; 16.123 + uart_tx_valid <= #1 `FALSE; 16.124 + uart_rx_byte <= #1 8'h00; 16.125 + uart_rx_valid <= #1 `FALSE; 16.126 `endif 16.127 end 16.128 else 16.129 @@ -298,13 +319,13 @@ 16.130 `LM32_CSR_JTX: 16.131 begin 16.132 // Set flag indicating data is available 16.133 - uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 16.134 - uart_tx_valid <= `TRUE; 16.135 + uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG]; 16.136 + uart_tx_valid <= #1 `TRUE; 16.137 end 16.138 `LM32_CSR_JRX: 16.139 begin 16.140 // Clear flag indidicating data has been received 16.141 - uart_rx_valid <= `FALSE; 16.142 + uart_rx_valid <= #1 `FALSE; 16.143 end 16.144 endcase 16.145 end 16.146 @@ -313,8 +334,8 @@ 16.147 // When an exception has occured, clear the requests 16.148 if (exception_q_w == `TRUE) 16.149 begin 16.150 - jtag_break <= `FALSE; 16.151 - jtag_reset <= `FALSE; 16.152 + jtag_break <= #1 `FALSE; 16.153 + jtag_reset <= #1 `FALSE; 16.154 end 16.155 `endif 16.156 case (state) 16.157 @@ -323,7 +344,7 @@ 16.158 // Wait for rx register to toggle which indicates new data is available 16.159 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.160 begin 16.161 - command <= rx_byte[7:4]; 16.162 + command <= #1 rx_byte[7:4]; 16.163 case (rx_addr) 16.164 `ifdef CFG_DEBUG_ENABLED 16.165 `LM32_DP: 16.166 @@ -331,37 +352,37 @@ 16.167 case (rx_byte[7:4]) 16.168 `ifdef CFG_HW_DEBUG_ENABLED 16.169 `LM32_DP_READ_MEMORY: 16.170 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.171 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.172 `LM32_DP_READ_SEQUENTIAL: 16.173 begin 16.174 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.175 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.176 + {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 16.177 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.178 end 16.179 `LM32_DP_WRITE_MEMORY: 16.180 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.181 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.182 `LM32_DP_WRITE_SEQUENTIAL: 16.183 begin 16.184 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.185 - state <= 5; 16.186 + {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 16.187 + state <= #1 5; 16.188 end 16.189 `LM32_DP_WRITE_CSR: 16.190 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.191 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.192 `endif 16.193 `LM32_DP_BREAK: 16.194 begin 16.195 `ifdef CFG_JTAG_UART_ENABLED 16.196 - uart_rx_valid <= `FALSE; 16.197 - uart_tx_valid <= `FALSE; 16.198 + uart_rx_valid <= #1 `FALSE; 16.199 + uart_tx_valid <= #1 `FALSE; 16.200 `endif 16.201 - jtag_break <= `TRUE; 16.202 + jtag_break <= #1 `TRUE; 16.203 end 16.204 `LM32_DP_RESET: 16.205 begin 16.206 `ifdef CFG_JTAG_UART_ENABLED 16.207 - uart_rx_valid <= `FALSE; 16.208 - uart_tx_valid <= `FALSE; 16.209 + uart_rx_valid <= #1 `FALSE; 16.210 + uart_tx_valid <= #1 `FALSE; 16.211 `endif 16.212 - jtag_reset <= `TRUE; 16.213 + jtag_reset <= #1 `TRUE; 16.214 end 16.215 endcase 16.216 end 16.217 @@ -369,13 +390,13 @@ 16.218 `ifdef CFG_JTAG_UART_ENABLED 16.219 `LM32_TX: 16.220 begin 16.221 - uart_rx_byte <= rx_byte; 16.222 - uart_rx_valid <= `TRUE; 16.223 + uart_rx_byte <= #1 rx_byte; 16.224 + uart_rx_valid <= #1 `TRUE; 16.225 end 16.226 `LM32_RX: 16.227 begin 16.228 - jtag_reg_d <= uart_tx_byte; 16.229 - uart_tx_valid <= `FALSE; 16.230 + jtag_reg_d <= #1 uart_tx_byte; 16.231 + uart_tx_valid <= #1 `FALSE; 16.232 end 16.233 `endif 16.234 default: 16.235 @@ -388,43 +409,43 @@ 16.236 begin 16.237 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.238 begin 16.239 - jtag_byte_0 <= rx_byte; 16.240 - state <= `LM32_JTAG_STATE_READ_BYTE_1; 16.241 + jtag_byte_0 <= #1 rx_byte; 16.242 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_1; 16.243 end 16.244 end 16.245 `LM32_JTAG_STATE_READ_BYTE_1: 16.246 begin 16.247 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.248 begin 16.249 - jtag_byte_1 <= rx_byte; 16.250 - state <= `LM32_JTAG_STATE_READ_BYTE_2; 16.251 + jtag_byte_1 <= #1 rx_byte; 16.252 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_2; 16.253 end 16.254 end 16.255 `LM32_JTAG_STATE_READ_BYTE_2: 16.256 begin 16.257 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.258 begin 16.259 - jtag_byte_2 <= rx_byte; 16.260 - state <= `LM32_JTAG_STATE_READ_BYTE_3; 16.261 + jtag_byte_2 <= #1 rx_byte; 16.262 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_3; 16.263 end 16.264 end 16.265 `LM32_JTAG_STATE_READ_BYTE_3: 16.266 begin 16.267 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.268 begin 16.269 - jtag_byte_3 <= rx_byte; 16.270 + jtag_byte_3 <= #1 rx_byte; 16.271 if (command == `LM32_DP_READ_MEMORY) 16.272 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.273 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.274 else 16.275 - state <= `LM32_JTAG_STATE_READ_BYTE_4; 16.276 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_4; 16.277 end 16.278 end 16.279 `LM32_JTAG_STATE_READ_BYTE_4: 16.280 begin 16.281 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.282 begin 16.283 - jtag_byte_4 <= rx_byte; 16.284 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.285 + jtag_byte_4 <= #1 rx_byte; 16.286 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.287 end 16.288 end 16.289 `LM32_JTAG_STATE_PROCESS_COMMAND: 16.290 @@ -433,22 +454,22 @@ 16.291 `LM32_DP_READ_MEMORY, 16.292 `LM32_DP_READ_SEQUENTIAL: 16.293 begin 16.294 - jtag_read_enable <= `TRUE; 16.295 - processing <= `TRUE; 16.296 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.297 + jtag_read_enable <= #1 `TRUE; 16.298 + processing <= #1 `TRUE; 16.299 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.300 end 16.301 `LM32_DP_WRITE_MEMORY, 16.302 `LM32_DP_WRITE_SEQUENTIAL: 16.303 begin 16.304 - jtag_write_enable <= `TRUE; 16.305 - processing <= `TRUE; 16.306 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.307 + jtag_write_enable <= #1 `TRUE; 16.308 + processing <= #1 `TRUE; 16.309 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.310 end 16.311 `LM32_DP_WRITE_CSR: 16.312 begin 16.313 - jtag_csr_write_enable <= `TRUE; 16.314 - processing <= `TRUE; 16.315 - state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 16.316 + jtag_csr_write_enable <= #1 `TRUE; 16.317 + processing <= #1 `TRUE; 16.318 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR; 16.319 end 16.320 endcase 16.321 end 16.322 @@ -456,18 +477,18 @@ 16.323 begin 16.324 if (jtag_access_complete == `TRUE) 16.325 begin 16.326 - jtag_read_enable <= `FALSE; 16.327 - jtag_reg_d <= jtag_read_data; 16.328 - jtag_write_enable <= `FALSE; 16.329 - processing <= `FALSE; 16.330 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.331 + jtag_read_enable <= #1 `FALSE; 16.332 + jtag_reg_d <= #1 jtag_read_data; 16.333 + jtag_write_enable <= #1 `FALSE; 16.334 + processing <= #1 `FALSE; 16.335 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.336 end 16.337 end 16.338 `LM32_JTAG_STATE_WAIT_FOR_CSR: 16.339 begin 16.340 - jtag_csr_write_enable <= `FALSE; 16.341 - processing <= `FALSE; 16.342 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.343 + jtag_csr_write_enable <= #1 `FALSE; 16.344 + processing <= #1 `FALSE; 16.345 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.346 end 16.347 `endif 16.348 endcase
17.1 --- a/lm32_load_store_unit.v Sun Mar 06 21:14:43 2011 +0000 17.2 +++ b/lm32_load_store_unit.v Sat Aug 06 00:02:46 2011 +0100 17.3 @@ -1,18 +1,39 @@ 17.4 -// ============================================================================= 17.5 -// COPYRIGHT NOTICE 17.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 17.7 -// ALL RIGHTS RESERVED 17.8 -// This confidential and proprietary software may be used only as authorised by 17.9 -// a licensing agreement from Lattice Semiconductor Corporation. 17.10 -// The entire notice above must be reproduced on all authorized copies and 17.11 -// copies may only be made to the extent permitted by a licensing agreement from 17.12 -// Lattice Semiconductor Corporation. 17.13 +// ================================================================== 17.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 17.15 +// ------------------------------------------------------------------ 17.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 17.17 +// ALL RIGHTS RESERVED 17.18 +// ------------------------------------------------------------------ 17.19 +// 17.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 17.21 +// 17.22 +// Permission: 17.23 +// 17.24 +// Lattice Semiconductor grants permission to use this code 17.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 17.26 +// Open Source License Agreement. 17.27 +// 17.28 +// Disclaimer: 17.29 // 17.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 17.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 17.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 17.33 -// U.S.A email: techsupport@latticesemi.com 17.34 -// =============================================================================/ 17.35 +// Lattice Semiconductor provides no warranty regarding the use or 17.36 +// functionality of this code. It is the user's responsibility to 17.37 +// verify the user’s design for consistency and functionality through 17.38 +// the use of formal verification methods. 17.39 +// 17.40 +// -------------------------------------------------------------------- 17.41 +// 17.42 +// Lattice Semiconductor Corporation 17.43 +// 5555 NE Moore Court 17.44 +// Hillsboro, OR 97214 17.45 +// U.S.A 17.46 +// 17.47 +// TEL: 1-800-Lattice (USA and Canada) 17.48 +// 503-286-8001 (other locations) 17.49 +// 17.50 +// web: http://www.latticesemi.com/ 17.51 +// email: techsupport@latticesemi.com 17.52 +// 17.53 +// -------------------------------------------------------------------- 17.54 // FILE DETAILS 17.55 // Project : LatticeMico32 17.56 // File : lm32_load_store_unit.v 17.57 @@ -302,8 +323,8 @@ 17.58 .ResetB (rst_i), 17.59 .DataInA ({32{1'b0}}), 17.60 .DataInB (dram_store_data_m), 17.61 - .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.62 - .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.63 + .AddressA (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), 17.64 + .AddressB (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), 17.65 // .ClockEnA (!stall_x & (load_x | store_x)), 17.66 .ClockEnA (!stall_x), 17.67 .ClockEnB (!stall_m), 17.68 @@ -322,13 +343,13 @@ 17.69 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.70 if (rst_i == `TRUE) 17.71 begin 17.72 - dram_bypass_en <= `FALSE; 17.73 - dram_bypass_data <= 0; 17.74 + dram_bypass_en <= #1 `FALSE; 17.75 + dram_bypass_data <= #1 0; 17.76 end 17.77 else 17.78 begin 17.79 if (stall_x == `FALSE) 17.80 - dram_bypass_data <= dram_store_data_m; 17.81 + dram_bypass_data <= #1 dram_store_data_m; 17.82 17.83 if ( (stall_m == `FALSE) 17.84 && (stall_x == `FALSE) 17.85 @@ -338,12 +359,12 @@ 17.86 ) 17.87 && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 17.88 ) 17.89 - dram_bypass_en <= `TRUE; 17.90 + dram_bypass_en <= #1 `TRUE; 17.91 else 17.92 if ( (dram_bypass_en == `TRUE) 17.93 && (stall_x == `FALSE) 17.94 ) 17.95 - dram_bypass_en <= `FALSE; 17.96 + dram_bypass_en <= #1 `FALSE; 17.97 end 17.98 17.99 assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 17.100 @@ -603,26 +624,26 @@ 17.101 begin 17.102 if (rst_i == `TRUE) 17.103 begin 17.104 - d_cyc_o <= `FALSE; 17.105 - d_stb_o <= `FALSE; 17.106 - d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.107 - d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.108 - d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 17.109 - d_we_o <= `FALSE; 17.110 - d_cti_o <= `LM32_CTYPE_END; 17.111 - d_lock_o <= `FALSE; 17.112 - wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.113 - wb_load_complete <= `FALSE; 17.114 - stall_wb_load <= `FALSE; 17.115 + d_cyc_o <= #1 `FALSE; 17.116 + d_stb_o <= #1 `FALSE; 17.117 + d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.118 + d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.119 + d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 17.120 + d_we_o <= #1 `FALSE; 17.121 + d_cti_o <= #1 `LM32_CTYPE_END; 17.122 + d_lock_o <= #1 `FALSE; 17.123 + wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.124 + wb_load_complete <= #1 `FALSE; 17.125 + stall_wb_load <= #1 `FALSE; 17.126 `ifdef CFG_DCACHE_ENABLED 17.127 - dcache_refill_ready <= `FALSE; 17.128 + dcache_refill_ready <= #1 `FALSE; 17.129 `endif 17.130 end 17.131 else 17.132 begin 17.133 `ifdef CFG_DCACHE_ENABLED 17.134 // Refill ready should only be asserted for a single cycle 17.135 - dcache_refill_ready <= `FALSE; 17.136 + dcache_refill_ready <= #1 `FALSE; 17.137 `endif 17.138 // Is a Wishbone cycle already in progress? 17.139 if (d_cyc_o == `TRUE) 17.140 @@ -634,25 +655,25 @@ 17.141 if ((dcache_refilling == `TRUE) && (!last_word)) 17.142 begin 17.143 // Fetch next word of cache line 17.144 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 17.145 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 17.146 end 17.147 else 17.148 `endif 17.149 begin 17.150 // Refill/access complete 17.151 - d_cyc_o <= `FALSE; 17.152 - d_stb_o <= `FALSE; 17.153 - d_lock_o <= `FALSE; 17.154 + d_cyc_o <= #1 `FALSE; 17.155 + d_stb_o <= #1 `FALSE; 17.156 + d_lock_o <= #1 `FALSE; 17.157 end 17.158 `ifdef CFG_DCACHE_ENABLED 17.159 - d_cti_o <= next_cycle_type; 17.160 + d_cti_o <= #1 next_cycle_type; 17.161 // If we are performing a refill, indicate to cache next word of data is ready 17.162 - dcache_refill_ready <= dcache_refilling; 17.163 + dcache_refill_ready <= #1 dcache_refilling; 17.164 `endif 17.165 // Register data read from Wishbone interface 17.166 - wb_data_m <= d_dat_i; 17.167 + wb_data_m <= #1 d_dat_i; 17.168 // Don't set when stores complete - otherwise we'll deadlock if load in m stage 17.169 - wb_load_complete <= !d_we_o; 17.170 + wb_load_complete <= #1 !d_we_o; 17.171 end 17.172 // synthesis translate_off 17.173 if (d_err_i == `TRUE) 17.174 @@ -665,13 +686,13 @@ 17.175 if (dcache_refill_request == `TRUE) 17.176 begin 17.177 // Start cache refill 17.178 - d_adr_o <= first_address; 17.179 - d_cyc_o <= `TRUE; 17.180 - d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 17.181 - d_stb_o <= `TRUE; 17.182 - d_we_o <= `FALSE; 17.183 - d_cti_o <= first_cycle_type; 17.184 - //d_lock_o <= `TRUE; 17.185 + d_adr_o <= #1 first_address; 17.186 + d_cyc_o <= #1 `TRUE; 17.187 + d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}}; 17.188 + d_stb_o <= #1 `TRUE; 17.189 + d_we_o <= #1 `FALSE; 17.190 + d_cti_o <= #1 first_cycle_type; 17.191 + //d_lock_o <= #1 `TRUE; 17.192 end 17.193 else 17.194 `endif 17.195 @@ -686,13 +707,13 @@ 17.196 ) 17.197 begin 17.198 // Data cache is write through, so all stores go to memory 17.199 - d_dat_o <= store_data_m; 17.200 - d_adr_o <= load_store_address_m; 17.201 - d_cyc_o <= `TRUE; 17.202 - d_sel_o <= byte_enable_m; 17.203 - d_stb_o <= `TRUE; 17.204 - d_we_o <= `TRUE; 17.205 - d_cti_o <= `LM32_CTYPE_END; 17.206 + d_dat_o <= #1 store_data_m; 17.207 + d_adr_o <= #1 load_store_address_m; 17.208 + d_cyc_o <= #1 `TRUE; 17.209 + d_sel_o <= #1 byte_enable_m; 17.210 + d_stb_o <= #1 `TRUE; 17.211 + d_we_o <= #1 `TRUE; 17.212 + d_cti_o <= #1 `LM32_CTYPE_END; 17.213 end 17.214 else if ( (load_q_m == `TRUE) 17.215 && (wb_select_m == `TRUE) 17.216 @@ -701,24 +722,24 @@ 17.217 ) 17.218 begin 17.219 // Read requested address 17.220 - stall_wb_load <= `FALSE; 17.221 - d_adr_o <= load_store_address_m; 17.222 - d_cyc_o <= `TRUE; 17.223 - d_sel_o <= byte_enable_m; 17.224 - d_stb_o <= `TRUE; 17.225 - d_we_o <= `FALSE; 17.226 - d_cti_o <= `LM32_CTYPE_END; 17.227 + stall_wb_load <= #1 `FALSE; 17.228 + d_adr_o <= #1 load_store_address_m; 17.229 + d_cyc_o <= #1 `TRUE; 17.230 + d_sel_o <= #1 byte_enable_m; 17.231 + d_stb_o <= #1 `TRUE; 17.232 + d_we_o <= #1 `FALSE; 17.233 + d_cti_o <= #1 `LM32_CTYPE_END; 17.234 end 17.235 end 17.236 // Clear load/store complete flag when instruction leaves M stage 17.237 if (stall_m == `FALSE) 17.238 - wb_load_complete <= `FALSE; 17.239 + wb_load_complete <= #1 `FALSE; 17.240 // When a Wishbone load first enters the M stage, we need to stall it 17.241 if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 17.242 - stall_wb_load <= `TRUE; 17.243 + stall_wb_load <= #1 `TRUE; 17.244 // Clear stall request if load instruction is killed 17.245 if ((kill_m == `TRUE) || (exception_m == `TRUE)) 17.246 - stall_wb_load <= `FALSE; 17.247 + stall_wb_load <= #1 `FALSE; 17.248 end 17.249 end 17.250 17.251 @@ -729,39 +750,39 @@ 17.252 begin 17.253 if (rst_i == `TRUE) 17.254 begin 17.255 - sign_extend_m <= `FALSE; 17.256 - size_m <= 2'b00; 17.257 - byte_enable_m <= `FALSE; 17.258 - store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.259 + sign_extend_m <= #1 `FALSE; 17.260 + size_m <= #1 2'b00; 17.261 + byte_enable_m <= #1 `FALSE; 17.262 + store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.263 `ifdef CFG_DCACHE_ENABLED 17.264 - dcache_select_m <= `FALSE; 17.265 + dcache_select_m <= #1 `FALSE; 17.266 `endif 17.267 `ifdef CFG_DRAM_ENABLED 17.268 - dram_select_m <= `FALSE; 17.269 + dram_select_m <= #1 `FALSE; 17.270 `endif 17.271 `ifdef CFG_IROM_ENABLED 17.272 - irom_select_m <= `FALSE; 17.273 + irom_select_m <= #1 `FALSE; 17.274 `endif 17.275 - wb_select_m <= `FALSE; 17.276 + wb_select_m <= #1 `FALSE; 17.277 end 17.278 else 17.279 begin 17.280 if (stall_m == `FALSE) 17.281 begin 17.282 - sign_extend_m <= sign_extend_x; 17.283 - size_m <= size_x; 17.284 - byte_enable_m <= byte_enable_x; 17.285 - store_data_m <= store_data_x; 17.286 + sign_extend_m <= #1 sign_extend_x; 17.287 + size_m <= #1 size_x; 17.288 + byte_enable_m <= #1 byte_enable_x; 17.289 + store_data_m <= #1 store_data_x; 17.290 `ifdef CFG_DCACHE_ENABLED 17.291 - dcache_select_m <= dcache_select_x; 17.292 + dcache_select_m <= #1 dcache_select_x; 17.293 `endif 17.294 `ifdef CFG_DRAM_ENABLED 17.295 - dram_select_m <= dram_select_x; 17.296 + dram_select_m <= #1 dram_select_x; 17.297 `endif 17.298 `ifdef CFG_IROM_ENABLED 17.299 - irom_select_m <= irom_select_x; 17.300 + irom_select_m <= #1 irom_select_x; 17.301 `endif 17.302 - wb_select_m <= wb_select_x; 17.303 + wb_select_m <= #1 wb_select_x; 17.304 end 17.305 end 17.306 end 17.307 @@ -771,15 +792,15 @@ 17.308 begin 17.309 if (rst_i == `TRUE) 17.310 begin 17.311 - size_w <= 2'b00; 17.312 - data_w <= {`LM32_WORD_WIDTH{1'b0}}; 17.313 - sign_extend_w <= `FALSE; 17.314 + size_w <= #1 2'b00; 17.315 + data_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.316 + sign_extend_w <= #1 `FALSE; 17.317 end 17.318 else 17.319 begin 17.320 - size_w <= size_m; 17.321 - data_w <= data_m; 17.322 - sign_extend_w <= sign_extend_m; 17.323 + size_w <= #1 size_m; 17.324 + data_w <= #1 data_m; 17.325 + sign_extend_w <= #1 sign_extend_m; 17.326 end 17.327 end 17.328
18.1 --- a/lm32_logic_op.v Sun Mar 06 21:14:43 2011 +0000 18.2 +++ b/lm32_logic_op.v Sat Aug 06 00:02:46 2011 +0100 18.3 @@ -1,18 +1,39 @@ 18.4 -// ============================================================================= 18.5 -// COPYRIGHT NOTICE 18.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 18.7 -// ALL RIGHTS RESERVED 18.8 -// This confidential and proprietary software may be used only as authorised by 18.9 -// a licensing agreement from Lattice Semiconductor Corporation. 18.10 -// The entire notice above must be reproduced on all authorized copies and 18.11 -// copies may only be made to the extent permitted by a licensing agreement from 18.12 -// Lattice Semiconductor Corporation. 18.13 +// ================================================================== 18.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 18.15 +// ------------------------------------------------------------------ 18.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 18.17 +// ALL RIGHTS RESERVED 18.18 +// ------------------------------------------------------------------ 18.19 +// 18.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 18.21 +// 18.22 +// Permission: 18.23 +// 18.24 +// Lattice Semiconductor grants permission to use this code 18.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 18.26 +// Open Source License Agreement. 18.27 +// 18.28 +// Disclaimer: 18.29 // 18.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 18.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 18.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 18.33 -// U.S.A email: techsupport@latticesemi.com 18.34 -// =============================================================================/ 18.35 +// Lattice Semiconductor provides no warranty regarding the use or 18.36 +// functionality of this code. It is the user's responsibility to 18.37 +// verify the user’s design for consistency and functionality through 18.38 +// the use of formal verification methods. 18.39 +// 18.40 +// -------------------------------------------------------------------- 18.41 +// 18.42 +// Lattice Semiconductor Corporation 18.43 +// 5555 NE Moore Court 18.44 +// Hillsboro, OR 97214 18.45 +// U.S.A 18.46 +// 18.47 +// TEL: 1-800-Lattice (USA and Canada) 18.48 +// 503-286-8001 (other locations) 18.49 +// 18.50 +// web: http://www.latticesemi.com/ 18.51 +// email: techsupport@latticesemi.com 18.52 +// 18.53 +// -------------------------------------------------------------------- 18.54 // FILE DETAILS 18.55 // Project : LatticeMico32 18.56 // File : lm32_logic_op.v
19.1 --- a/lm32_mc_arithmetic.v Sun Mar 06 21:14:43 2011 +0000 19.2 +++ b/lm32_mc_arithmetic.v Sat Aug 06 00:02:46 2011 +0100 19.3 @@ -1,18 +1,39 @@ 19.4 -// ============================================================================= 19.5 -// COPYRIGHT NOTICE 19.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 19.7 -// ALL RIGHTS RESERVED 19.8 -// This confidential and proprietary software may be used only as authorised by 19.9 -// a licensing agreement from Lattice Semiconductor Corporation. 19.10 -// The entire notice above must be reproduced on all authorized copies and 19.11 -// copies may only be made to the extent permitted by a licensing agreement from 19.12 -// Lattice Semiconductor Corporation. 19.13 +// ================================================================== 19.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 19.15 +// ------------------------------------------------------------------ 19.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 19.17 +// ALL RIGHTS RESERVED 19.18 +// ------------------------------------------------------------------ 19.19 +// 19.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 19.21 +// 19.22 +// Permission: 19.23 +// 19.24 +// Lattice Semiconductor grants permission to use this code 19.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 19.26 +// Open Source License Agreement. 19.27 +// 19.28 +// Disclaimer: 19.29 // 19.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 19.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 19.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 19.33 -// U.S.A email: techsupport@latticesemi.com 19.34 -// =============================================================================/ 19.35 +// Lattice Semiconductor provides no warranty regarding the use or 19.36 +// functionality of this code. It is the user's responsibility to 19.37 +// verify the user’s design for consistency and functionality through 19.38 +// the use of formal verification methods. 19.39 +// 19.40 +// -------------------------------------------------------------------- 19.41 +// 19.42 +// Lattice Semiconductor Corporation 19.43 +// 5555 NE Moore Court 19.44 +// Hillsboro, OR 97214 19.45 +// U.S.A 19.46 +// 19.47 +// TEL: 1-800-Lattice (USA and Canada) 19.48 +// 503-286-8001 (other locations) 19.49 +// 19.50 +// web: http://www.latticesemi.com/ 19.51 +// email: techsupport@latticesemi.com 19.52 +// 19.53 +// -------------------------------------------------------------------- 19.54 // FILE DETAILS 19.55 // Project : LatticeMico32 19.56 // File : lm_mc_arithmetic.v 19.57 @@ -149,59 +170,59 @@ 19.58 begin 19.59 if (rst_i == `TRUE) 19.60 begin 19.61 - cycles <= {6{1'b0}}; 19.62 - p <= {`LM32_WORD_WIDTH{1'b0}}; 19.63 - a <= {`LM32_WORD_WIDTH{1'b0}}; 19.64 - b <= {`LM32_WORD_WIDTH{1'b0}}; 19.65 + cycles <= #1 {6{1'b0}}; 19.66 + p <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.67 + a <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.68 + b <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.69 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.70 - sign_extend_x <= 1'b0; 19.71 + sign_extend_x <= #1 1'b0; 19.72 `endif 19.73 `ifdef CFG_MC_DIVIDE_ENABLED 19.74 - divide_by_zero_x <= `FALSE; 19.75 + divide_by_zero_x <= #1 `FALSE; 19.76 `endif 19.77 - result_x <= {`LM32_WORD_WIDTH{1'b0}}; 19.78 - state <= `LM32_MC_STATE_IDLE; 19.79 + result_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.80 + state <= #1 `LM32_MC_STATE_IDLE; 19.81 end 19.82 else 19.83 begin 19.84 `ifdef CFG_MC_DIVIDE_ENABLED 19.85 - divide_by_zero_x <= `FALSE; 19.86 + divide_by_zero_x <= #1 `FALSE; 19.87 `endif 19.88 case (state) 19.89 `LM32_MC_STATE_IDLE: 19.90 begin 19.91 if (stall_d == `FALSE) 19.92 begin 19.93 - cycles <= `LM32_WORD_WIDTH; 19.94 - p <= 32'b0; 19.95 - a <= operand_0_d; 19.96 - b <= operand_1_d; 19.97 + cycles <= #1 `LM32_WORD_WIDTH; 19.98 + p <= #1 32'b0; 19.99 + a <= #1 operand_0_d; 19.100 + b <= #1 operand_1_d; 19.101 `ifdef CFG_MC_DIVIDE_ENABLED 19.102 if (divide_d == `TRUE) 19.103 - state <= `LM32_MC_STATE_DIVIDE; 19.104 + state <= #1 `LM32_MC_STATE_DIVIDE; 19.105 if (modulus_d == `TRUE) 19.106 - state <= `LM32_MC_STATE_MODULUS; 19.107 + state <= #1 `LM32_MC_STATE_MODULUS; 19.108 `endif 19.109 `ifdef CFG_MC_MULTIPLY_ENABLED 19.110 if (multiply_d == `TRUE) 19.111 - state <= `LM32_MC_STATE_MULTIPLY; 19.112 + state <= #1 `LM32_MC_STATE_MULTIPLY; 19.113 `endif 19.114 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.115 if (shift_left_d == `TRUE) 19.116 begin 19.117 - state <= `LM32_MC_STATE_SHIFT_LEFT; 19.118 - sign_extend_x <= sign_extend_d; 19.119 - cycles <= operand_1_d[4:0]; 19.120 - a <= operand_0_d; 19.121 - b <= operand_0_d; 19.122 + state <= #1 `LM32_MC_STATE_SHIFT_LEFT; 19.123 + sign_extend_x <= #1 sign_extend_d; 19.124 + cycles <= #1 operand_1_d[4:0]; 19.125 + a <= #1 operand_0_d; 19.126 + b <= #1 operand_0_d; 19.127 end 19.128 if (shift_right_d == `TRUE) 19.129 begin 19.130 - state <= `LM32_MC_STATE_SHIFT_RIGHT; 19.131 - sign_extend_x <= sign_extend_d; 19.132 - cycles <= operand_1_d[4:0]; 19.133 - a <= operand_0_d; 19.134 - b <= operand_0_d; 19.135 + state <= #1 `LM32_MC_STATE_SHIFT_RIGHT; 19.136 + sign_extend_x <= #1 sign_extend_d; 19.137 + cycles <= #1 operand_1_d[4:0]; 19.138 + a <= #1 operand_0_d; 19.139 + b <= #1 operand_0_d; 19.140 end 19.141 `endif 19.142 end 19.143 @@ -211,74 +232,74 @@ 19.144 begin 19.145 if (t[32] == 1'b0) 19.146 begin 19.147 - p <= t[31:0]; 19.148 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.149 + p <= #1 t[31:0]; 19.150 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.151 end 19.152 else 19.153 begin 19.154 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.155 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.156 + p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.157 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.158 end 19.159 - result_x <= a; 19.160 + result_x <= #1 a; 19.161 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.162 begin 19.163 // Check for divide by zero 19.164 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.165 - state <= `LM32_MC_STATE_IDLE; 19.166 + divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 19.167 + state <= #1 `LM32_MC_STATE_IDLE; 19.168 end 19.169 - cycles <= cycles - 1'b1; 19.170 + cycles <= #1 cycles - 1'b1; 19.171 end 19.172 `LM32_MC_STATE_MODULUS: 19.173 begin 19.174 if (t[32] == 1'b0) 19.175 begin 19.176 - p <= t[31:0]; 19.177 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.178 + p <= #1 t[31:0]; 19.179 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.180 end 19.181 else 19.182 begin 19.183 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.184 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.185 + p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.186 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.187 end 19.188 - result_x <= p; 19.189 + result_x <= #1 p; 19.190 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.191 begin 19.192 // Check for divide by zero 19.193 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.194 - state <= `LM32_MC_STATE_IDLE; 19.195 + divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 19.196 + state <= #1 `LM32_MC_STATE_IDLE; 19.197 end 19.198 - cycles <= cycles - 1'b1; 19.199 + cycles <= #1 cycles - 1'b1; 19.200 end 19.201 `endif 19.202 `ifdef CFG_MC_MULTIPLY_ENABLED 19.203 `LM32_MC_STATE_MULTIPLY: 19.204 begin 19.205 if (b[0] == 1'b1) 19.206 - p <= p + a; 19.207 - b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 19.208 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.209 - result_x <= p; 19.210 + p <= #1 p + a; 19.211 + b <= #1 {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 19.212 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.213 + result_x <= #1 p; 19.214 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.215 - state <= `LM32_MC_STATE_IDLE; 19.216 - cycles <= cycles - 1'b1; 19.217 + state <= #1 `LM32_MC_STATE_IDLE; 19.218 + cycles <= #1 cycles - 1'b1; 19.219 end 19.220 `endif 19.221 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.222 `LM32_MC_STATE_SHIFT_LEFT: 19.223 begin 19.224 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.225 - result_x <= a; 19.226 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.227 + result_x <= #1 a; 19.228 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.229 - state <= `LM32_MC_STATE_IDLE; 19.230 - cycles <= cycles - 1'b1; 19.231 + state <= #1 `LM32_MC_STATE_IDLE; 19.232 + cycles <= #1 cycles - 1'b1; 19.233 end 19.234 `LM32_MC_STATE_SHIFT_RIGHT: 19.235 begin 19.236 - b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 19.237 - result_x <= b; 19.238 + b <= #1 {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 19.239 + result_x <= #1 b; 19.240 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.241 - state <= `LM32_MC_STATE_IDLE; 19.242 - cycles <= cycles - 1'b1; 19.243 + state <= #1 `LM32_MC_STATE_IDLE; 19.244 + cycles <= #1 cycles - 1'b1; 19.245 end 19.246 `endif 19.247 endcase
20.1 --- a/lm32_monitor.v Sun Mar 06 21:14:43 2011 +0000 20.2 +++ b/lm32_monitor.v Sat Aug 06 00:02:46 2011 +0100 20.3 @@ -1,18 +1,39 @@ 20.4 -// ============================================================================= 20.5 -// COPYRIGHT NOTICE 20.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 20.7 -// ALL RIGHTS RESERVED 20.8 -// This confidential and proprietary software may be used only as authorised by 20.9 -// a licensing agreement from Lattice Semiconductor Corporation. 20.10 -// The entire notice above must be reproduced on all authorized copies and 20.11 -// copies may only be made to the extent permitted by a licensing agreement from 20.12 -// Lattice Semiconductor Corporation. 20.13 +// ================================================================== 20.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 20.15 +// ------------------------------------------------------------------ 20.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 20.17 +// ALL RIGHTS RESERVED 20.18 +// ------------------------------------------------------------------ 20.19 +// 20.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 20.21 +// 20.22 +// Permission: 20.23 +// 20.24 +// Lattice Semiconductor grants permission to use this code 20.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 20.26 +// Open Source License Agreement. 20.27 +// 20.28 +// Disclaimer: 20.29 // 20.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 20.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 20.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 20.33 -// U.S.A email: techsupport@latticesemi.com 20.34 -// =============================================================================/ 20.35 +// Lattice Semiconductor provides no warranty regarding the use or 20.36 +// functionality of this code. It is the user's responsibility to 20.37 +// verify the user’s design for consistency and functionality through 20.38 +// the use of formal verification methods. 20.39 +// 20.40 +// -------------------------------------------------------------------- 20.41 +// 20.42 +// Lattice Semiconductor Corporation 20.43 +// 5555 NE Moore Court 20.44 +// Hillsboro, OR 97214 20.45 +// U.S.A 20.46 +// 20.47 +// TEL: 1-800-Lattice (USA and Canada) 20.48 +// 503-286-8001 (other locations) 20.49 +// 20.50 +// web: http://www.latticesemi.com/ 20.51 +// email: techsupport@latticesemi.com 20.52 +// 20.53 +// -------------------------------------------------------------------- 20.54 // FILE DETAILS 20.55 // Project : LatticeMico32 20.56 // File : lm32_monitor.v 20.57 @@ -123,10 +144,10 @@ 20.58 begin 20.59 if (rst_i == `TRUE) 20.60 begin 20.61 - write_enable <= `FALSE; 20.62 - MON_ACK_O <= `FALSE; 20.63 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.64 - state <= 2'b00; 20.65 + write_enable <= #1 `FALSE; 20.66 + MON_ACK_O <= #1 `FALSE; 20.67 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 20.68 + state <= #1 2'b00; 20.69 end 20.70 else 20.71 begin 20.72 @@ -134,33 +155,33 @@ 20.73 2'b01: 20.74 begin 20.75 // Output read data to Wishbone 20.76 - MON_ACK_O <= `TRUE; 20.77 - MON_DAT_O <= data; 20.78 + MON_ACK_O <= #1 `TRUE; 20.79 + MON_DAT_O <= #1 data; 20.80 // Sub-word writes are performed using read-modify-write 20.81 // as the Lattice EBRs don't support byte enables 20.82 if (MON_WE_I == `TRUE) 20.83 - write_enable <= `TRUE; 20.84 - write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 20.85 - write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 20.86 - write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 20.87 - write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 20.88 - state <= 2'b10; 20.89 + write_enable <= #1 `TRUE; 20.90 + write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 20.91 + write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 20.92 + write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 20.93 + write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 20.94 + state <= #1 2'b10; 20.95 end 20.96 2'b10: 20.97 begin 20.98 // Wishbone access occurs in this cycle 20.99 - write_enable <= `FALSE; 20.100 - MON_ACK_O <= `FALSE; 20.101 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.102 - state <= 2'b00; 20.103 + write_enable <= #1 `FALSE; 20.104 + MON_ACK_O <= #1 `FALSE; 20.105 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 20.106 + state <= #1 2'b00; 20.107 end 20.108 default: 20.109 begin 20.110 - write_enable <= `FALSE; 20.111 - MON_ACK_O <= `FALSE; 20.112 + write_enable <= #1 `FALSE; 20.113 + MON_ACK_O <= #1 `FALSE; 20.114 // Wait for a Wishbone access 20.115 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 20.116 - state <= 2'b01; 20.117 + state <= #1 2'b01; 20.118 end 20.119 endcase 20.120 end
21.1 --- a/lm32_monitor_ram.v Sun Mar 06 21:14:43 2011 +0000 21.2 +++ b/lm32_monitor_ram.v Sat Aug 06 00:02:46 2011 +0100 21.3 @@ -1,18 +1,39 @@ 21.4 -// ============================================================================= 21.5 -// COPYRIGHT NOTICE 21.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 21.7 -// ALL RIGHTS RESERVED 21.8 -// This confidential and proprietary software may be used only as authorised by 21.9 -// a licensing agreement from Lattice Semiconductor Corporation. 21.10 -// The entire notice above must be reproduced on all authorized copies and 21.11 -// copies may only be made to the extent permitted by a licensing agreement from 21.12 -// Lattice Semiconductor Corporation. 21.13 +// ================================================================== 21.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 21.15 +// ------------------------------------------------------------------ 21.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 21.17 +// ALL RIGHTS RESERVED 21.18 +// ------------------------------------------------------------------ 21.19 +// 21.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 21.21 +// 21.22 +// Permission: 21.23 +// 21.24 +// Lattice Semiconductor grants permission to use this code 21.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 21.26 +// Open Source License Agreement. 21.27 +// 21.28 +// Disclaimer: 21.29 // 21.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 21.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 21.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 21.33 -// U.S.A email: techsupport@latticesemi.com 21.34 -// =============================================================================/ 21.35 +// Lattice Semiconductor provides no warranty regarding the use or 21.36 +// functionality of this code. It is the user's responsibility to 21.37 +// verify the user’s design for consistency and functionality through 21.38 +// the use of formal verification methods. 21.39 +// 21.40 +// -------------------------------------------------------------------- 21.41 +// 21.42 +// Lattice Semiconductor Corporation 21.43 +// 5555 NE Moore Court 21.44 +// Hillsboro, OR 97214 21.45 +// U.S.A 21.46 +// 21.47 +// TEL: 1-800-Lattice (USA and Canada) 21.48 +// 503-286-8001 (other locations) 21.49 +// 21.50 +// web: http://www.latticesemi.com/ 21.51 +// email: techsupport@latticesemi.com 21.52 +// 21.53 +// -------------------------------------------------------------------- 21.54 // FILE DETAILS 21.55 // Project : LatticeMico32 21.56 // File : lm32_monitor_ram.v
22.1 --- a/lm32_multiplier.v Sun Mar 06 21:14:43 2011 +0000 22.2 +++ b/lm32_multiplier.v Sat Aug 06 00:02:46 2011 +0100 22.3 @@ -1,18 +1,39 @@ 22.4 -// ============================================================================= 22.5 -// COPYRIGHT NOTICE 22.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 22.7 -// ALL RIGHTS RESERVED 22.8 -// This confidential and proprietary software may be used only as authorised by 22.9 -// a licensing agreement from Lattice Semiconductor Corporation. 22.10 -// The entire notice above must be reproduced on all authorized copies and 22.11 -// copies may only be made to the extent permitted by a licensing agreement from 22.12 -// Lattice Semiconductor Corporation. 22.13 +// ================================================================== 22.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 22.15 +// ------------------------------------------------------------------ 22.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 22.17 +// ALL RIGHTS RESERVED 22.18 +// ------------------------------------------------------------------ 22.19 +// 22.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 22.21 +// 22.22 +// Permission: 22.23 +// 22.24 +// Lattice Semiconductor grants permission to use this code 22.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 22.26 +// Open Source License Agreement. 22.27 +// 22.28 +// Disclaimer: 22.29 // 22.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 22.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 22.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 22.33 -// U.S.A email: techsupport@latticesemi.com 22.34 -// =============================================================================/ 22.35 +// Lattice Semiconductor provides no warranty regarding the use or 22.36 +// functionality of this code. It is the user's responsibility to 22.37 +// verify the user’s design for consistency and functionality through 22.38 +// the use of formal verification methods. 22.39 +// 22.40 +// -------------------------------------------------------------------- 22.41 +// 22.42 +// Lattice Semiconductor Corporation 22.43 +// 5555 NE Moore Court 22.44 +// Hillsboro, OR 97214 22.45 +// U.S.A 22.46 +// 22.47 +// TEL: 1-800-Lattice (USA and Canada) 22.48 +// 503-286-8001 (other locations) 22.49 +// 22.50 +// web: http://www.latticesemi.com/ 22.51 +// email: techsupport@latticesemi.com 22.52 +// 22.53 +// -------------------------------------------------------------------- 22.54 // FILE DETAILS 22.55 // Project : LatticeMico32 22.56 // File : lm32_multiplier.v 22.57 @@ -78,21 +99,21 @@ 22.58 begin 22.59 if (rst_i == `TRUE) 22.60 begin 22.61 - muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 22.62 - multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 22.63 - product <= {`LM32_WORD_WIDTH{1'b0}}; 22.64 - result <= {`LM32_WORD_WIDTH{1'b0}}; 22.65 + muliplicand <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.66 + multiplier <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.67 + product <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.68 + result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.69 end 22.70 else 22.71 begin 22.72 if (stall_x == `FALSE) 22.73 begin 22.74 - muliplicand <= operand_0; 22.75 - multiplier <= operand_1; 22.76 + muliplicand <= #1 operand_0; 22.77 + multiplier <= #1 operand_1; 22.78 end 22.79 if (stall_m == `FALSE) 22.80 - product <= muliplicand * multiplier; 22.81 - result <= product; 22.82 + product <= #1 muliplicand * multiplier; 22.83 + result <= #1 product; 22.84 end 22.85 end 22.86
23.1 --- a/lm32_ram.v Sun Mar 06 21:14:43 2011 +0000 23.2 +++ b/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 23.3 @@ -1,18 +1,39 @@ 23.4 -// ============================================================================= 23.5 -// COPYRIGHT NOTICE 23.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 23.7 -// ALL RIGHTS RESERVED 23.8 -// This confidential and proprietary software may be used only as authorised by 23.9 -// a licensing agreement from Lattice Semiconductor Corporation. 23.10 -// The entire notice above must be reproduced on all authorized copies and 23.11 -// copies may only be made to the extent permitted by a licensing agreement from 23.12 -// Lattice Semiconductor Corporation. 23.13 +// ================================================================== 23.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 23.15 +// ------------------------------------------------------------------ 23.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 23.17 +// ALL RIGHTS RESERVED 23.18 +// ------------------------------------------------------------------ 23.19 +// 23.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 23.21 +// 23.22 +// Permission: 23.23 +// 23.24 +// Lattice Semiconductor grants permission to use this code 23.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 23.26 +// Open Source License Agreement. 23.27 +// 23.28 +// Disclaimer: 23.29 // 23.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 23.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 23.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 23.33 -// U.S.A email: techsupport@latticesemi.com 23.34 -// =============================================================================/ 23.35 +// Lattice Semiconductor provides no warranty regarding the use or 23.36 +// functionality of this code. It is the user's responsibility to 23.37 +// verify the user’s design for consistency and functionality through 23.38 +// the use of formal verification methods. 23.39 +// 23.40 +// -------------------------------------------------------------------- 23.41 +// 23.42 +// Lattice Semiconductor Corporation 23.43 +// 5555 NE Moore Court 23.44 +// Hillsboro, OR 97214 23.45 +// U.S.A 23.46 +// 23.47 +// TEL: 1-800-Lattice (USA and Canada) 23.48 +// 503-286-8001 (other locations) 23.49 +// 23.50 +// web: http://www.latticesemi.com/ 23.51 +// email: techsupport@latticesemi.com 23.52 +// 23.53 +// -------------------------------------------------------------------- 23.54 // FILE DETAILS 23.55 // Project : LatticeMico32 23.56 // File : lm32_ram.v 23.57 @@ -252,7 +273,7 @@ 23.58 23.59 always @(posedge read_clk) 23.60 if (enable_read) 23.61 - ra <= read_address; 23.62 + ra <= #1 read_address; 23.63 end 23.64 23.65 else 23.66 @@ -275,12 +296,12 @@ 23.67 // Write port 23.68 always @(posedge write_clk) 23.69 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 23.70 - mem[write_address] <= write_data; 23.71 + mem[write_address] <= #1 write_data; 23.72 23.73 // Register read address for use on next cycle 23.74 always @(posedge read_clk) 23.75 if (enable_read) 23.76 - ra <= read_address; 23.77 + ra <= #1 read_address; 23.78 23.79 end 23.80
24.1 --- a/lm32_shifter.v Sun Mar 06 21:14:43 2011 +0000 24.2 +++ b/lm32_shifter.v Sat Aug 06 00:02:46 2011 +0100 24.3 @@ -1,18 +1,39 @@ 24.4 -// ============================================================================= 24.5 -// COPYRIGHT NOTICE 24.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 24.7 -// ALL RIGHTS RESERVED 24.8 -// This confidential and proprietary software may be used only as authorised by 24.9 -// a licensing agreement from Lattice Semiconductor Corporation. 24.10 -// The entire notice above must be reproduced on all authorized copies and 24.11 -// copies may only be made to the extent permitted by a licensing agreement from 24.12 -// Lattice Semiconductor Corporation. 24.13 +// ================================================================== 24.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 24.15 +// ------------------------------------------------------------------ 24.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 24.17 +// ALL RIGHTS RESERVED 24.18 +// ------------------------------------------------------------------ 24.19 +// 24.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 24.21 +// 24.22 +// Permission: 24.23 +// 24.24 +// Lattice Semiconductor grants permission to use this code 24.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 24.26 +// Open Source License Agreement. 24.27 +// 24.28 +// Disclaimer: 24.29 // 24.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 24.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 24.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 24.33 -// U.S.A email: techsupport@latticesemi.com 24.34 -// =============================================================================/ 24.35 +// Lattice Semiconductor provides no warranty regarding the use or 24.36 +// functionality of this code. It is the user's responsibility to 24.37 +// verify the user’s design for consistency and functionality through 24.38 +// the use of formal verification methods. 24.39 +// 24.40 +// -------------------------------------------------------------------- 24.41 +// 24.42 +// Lattice Semiconductor Corporation 24.43 +// 5555 NE Moore Court 24.44 +// Hillsboro, OR 97214 24.45 +// U.S.A 24.46 +// 24.47 +// TEL: 1-800-Lattice (USA and Canada) 24.48 +// 503-286-8001 (other locations) 24.49 +// 24.50 +// web: http://www.latticesemi.com/ 24.51 +// email: techsupport@latticesemi.com 24.52 +// 24.53 +// -------------------------------------------------------------------- 24.54 // FILE DETAILS 24.55 // Project : LatticeMico32 24.56 // File : lm32_shifter.v 24.57 @@ -118,15 +139,15 @@ 24.58 begin 24.59 if (rst_i == `TRUE) 24.60 begin 24.61 - right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 24.62 - direction_m <= `FALSE; 24.63 + right_shift_result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 24.64 + direction_m <= #1 `FALSE; 24.65 end 24.66 else 24.67 begin 24.68 if (stall_x == `FALSE) 24.69 begin 24.70 - right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 24.71 - direction_m <= direction_x; 24.72 + right_shift_result <= #1 {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 24.73 + direction_m <= #1 direction_x; 24.74 end 24.75 end 24.76 end
25.1 --- a/lm32_top.v Sun Mar 06 21:14:43 2011 +0000 25.2 +++ b/lm32_top.v Sat Aug 06 00:02:46 2011 +0100 25.3 @@ -1,18 +1,39 @@ 25.4 -// ============================================================================= 25.5 -// COPYRIGHT NOTICE 25.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 25.7 -// ALL RIGHTS RESERVED 25.8 -// This confidential and proprietary software may be used only as authorised by 25.9 -// a licensing agreement from Lattice Semiconductor Corporation. 25.10 -// The entire notice above must be reproduced on all authorized copies and 25.11 -// copies may only be made to the extent permitted by a licensing agreement from 25.12 -// Lattice Semiconductor Corporation. 25.13 +// ================================================================== 25.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 25.15 +// ------------------------------------------------------------------ 25.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 25.17 +// ALL RIGHTS RESERVED 25.18 +// ------------------------------------------------------------------ 25.19 +// 25.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 25.21 +// 25.22 +// Permission: 25.23 +// 25.24 +// Lattice Semiconductor grants permission to use this code 25.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 25.26 +// Open Source License Agreement. 25.27 +// 25.28 +// Disclaimer: 25.29 // 25.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 25.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 25.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 25.33 -// U.S.A email: techsupport@latticesemi.com 25.34 -// =============================================================================/ 25.35 +// Lattice Semiconductor provides no warranty regarding the use or 25.36 +// functionality of this code. It is the user's responsibility to 25.37 +// verify the user’s design for consistency and functionality through 25.38 +// the use of formal verification methods. 25.39 +// 25.40 +// -------------------------------------------------------------------- 25.41 +// 25.42 +// Lattice Semiconductor Corporation 25.43 +// 5555 NE Moore Court 25.44 +// Hillsboro, OR 97214 25.45 +// U.S.A 25.46 +// 25.47 +// TEL: 1-800-Lattice (USA and Canada) 25.48 +// 503-286-8001 (other locations) 25.49 +// 25.50 +// web: http://www.latticesemi.com/ 25.51 +// email: techsupport@latticesemi.com 25.52 +// 25.53 +// -------------------------------------------------------------------- 25.54 // FILE DETAILS 25.55 // Project : LatticeMico32 25.56 // File : lm32_top.v 25.57 @@ -36,6 +57,11 @@ 25.58 // ----- Inputs ------- 25.59 clk_i, 25.60 rst_i, 25.61 +`ifdef CFG_DEBUG_ENABLED 25.62 + `ifdef CFG_ALTERNATE_EBA 25.63 + at_debug, 25.64 + `endif 25.65 +`endif 25.66 // From external devices 25.67 `ifdef CFG_INTERRUPTS_ENABLED 25.68 interrupt_n, 25.69 @@ -110,6 +136,12 @@ 25.70 input clk_i; // Clock 25.71 input rst_i; // Reset 25.72 25.73 +`ifdef CFG_DEBUG_ENABLED 25.74 + `ifdef CFG_ALTERNATE_EBA 25.75 + input at_debug; // GPIO input that maps EBA to DEBA 25.76 + `endif 25.77 +`endif 25.78 + 25.79 `ifdef CFG_INTERRUPTS_ENABLED 25.80 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 25.81 `endif 25.82 @@ -249,6 +281,11 @@ 25.83 .clk_n_i (clk_n), 25.84 `endif 25.85 .rst_i (rst_i), 25.86 +`ifdef CFG_DEBUG_ENABLED 25.87 + `ifdef CFG_ALTERNATE_EBA 25.88 + .at_debug (at_debug), 25.89 + `endif 25.90 +`endif 25.91 // From external devices 25.92 `ifdef CFG_INTERRUPTS_ENABLED 25.93 .interrupt_n (interrupt_n),
26.1 --- a/lm32_trace.v Sun Mar 06 21:14:43 2011 +0000 26.2 +++ b/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 26.3 @@ -1,18 +1,39 @@ 26.4 -// ============================================================================= 26.5 -// COPYRIGHT NOTICE 26.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 26.7 -// ALL RIGHTS RESERVED 26.8 -// This confidential and proprietary software may be used only as authorised by 26.9 -// a licensing agreement from Lattice Semiconductor Corporation. 26.10 -// The entire notice above must be reproduced on all authorized copies and 26.11 -// copies may only be made to the extent permitted by a licensing agreement from 26.12 -// Lattice Semiconductor Corporation. 26.13 +// ================================================================== 26.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 26.15 +// ------------------------------------------------------------------ 26.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 26.17 +// ALL RIGHTS RESERVED 26.18 +// ------------------------------------------------------------------ 26.19 +// 26.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 26.21 +// 26.22 +// Permission: 26.23 +// 26.24 +// Lattice Semiconductor grants permission to use this code 26.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 26.26 +// Open Source License Agreement. 26.27 +// 26.28 +// Disclaimer: 26.29 // 26.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 26.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 26.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 26.33 -// U.S.A email: techsupport@latticesemi.com 26.34 -// =============================================================================/ 26.35 +// Lattice Semiconductor provides no warranty regarding the use or 26.36 +// functionality of this code. It is the user's responsibility to 26.37 +// verify the user’s design for consistency and functionality through 26.38 +// the use of formal verification methods. 26.39 +// 26.40 +// -------------------------------------------------------------------- 26.41 +// 26.42 +// Lattice Semiconductor Corporation 26.43 +// 5555 NE Moore Court 26.44 +// Hillsboro, OR 97214 26.45 +// U.S.A 26.46 +// 26.47 +// TEL: 1-800-Lattice (USA and Canada) 26.48 +// 503-286-8001 (other locations) 26.49 +// 26.50 +// web: http://www.latticesemi.com/ 26.51 +// email: techsupport@latticesemi.com 26.52 +// 26.53 +// -------------------------------------------------------------------- 26.54 // FILE DETAILS 26.55 // Project : LatticeMico32 26.56 // File : lm32_trace.v 26.57 @@ -24,6 +45,8 @@ 26.58 // : No Change 26.59 // Version : 3.1 26.60 // : No Change 26.61 +// Version : 3.7 26.62 +// : Removed syntax error. 26.63 // ============================================================================= 26.64 26.65 `include "lm32_include.v" 26.66 @@ -123,65 +146,65 @@ 26.67 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 26.68 26.69 initial begin 26.70 - trig_type <= 0; 26.71 - stop_type <= 0; 26.72 - trace_len <= 0; 26.73 - pc_low <= 0; 26.74 - pc_high <= 0; 26.75 - trace_start <= 0; 26.76 - trace_stop <= 0; 26.77 - ack_o <= 0; 26.78 - reg_dat_o <= 0; 26.79 - mem_valid <= 0; 26.80 - started <= 0; 26.81 - capturing <= 0; 26.82 + trig_type <= #1 0; 26.83 + stop_type <= #1 0; 26.84 + trace_len <= #1 0; 26.85 + pc_low <= #1 0; 26.86 + pc_high <= #1 0; 26.87 + trace_start <= #1 0; 26.88 + trace_stop <= #1 0; 26.89 + ack_o <= #1 0; 26.90 + reg_dat_o <= #1 0; 26.91 + mem_valid <= #1 0; 26.92 + started <= #1 0; 26.93 + capturing <= #1 0; 26.94 end 26.95 26.96 // the host side control 26.97 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.98 begin 26.99 if (rst_i == `TRUE) begin 26.100 - trig_type <= 0; 26.101 - trace_stop <= 0; 26.102 - trace_start <= 0; 26.103 - pc_low <= 0; 26.104 - pc_high <= 0; 26.105 - ack_o <= 0; 26.106 + trig_type <= #1 0; 26.107 + trace_stop <= #1 0; 26.108 + trace_start <= #1 0; 26.109 + pc_low <= #1 0; 26.110 + pc_high <= #1 0; 26.111 + ack_o <= #1 0; 26.112 end else begin 26.113 if (stb_i == `TRUE && ack_o == `FALSE) begin 26.114 if (rw_creg) begin // control register access 26.115 - ack_o <= `TRUE; 26.116 + ack_o <= #1 `TRUE; 26.117 if (we_i == `TRUE) begin 26.118 case ({adr_i[11:2],2'b0}) 26.119 // write to trig type 26.120 12'd0: 26.121 begin 26.122 if (sel_i[0]) begin 26.123 - trig_type[4:0] <= dat_i[4:0]; 26.124 + trig_type[4:0] <= #1 dat_i[4:0]; 26.125 end 26.126 if (sel_i[3]) begin 26.127 - trace_start <= dat_i[31]; 26.128 - trace_stop <= dat_i[30]; 26.129 + trace_start <= #1 dat_i[31]; 26.130 + trace_stop <= #1 dat_i[30]; 26.131 end 26.132 end 26.133 12'd8: 26.134 begin 26.135 - if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 26.136 - if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 26.137 - if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 26.138 - if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 26.139 + if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 26.140 + if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 26.141 + if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 26.142 + if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 26.143 end 26.144 12'd12: 26.145 begin 26.146 - if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 26.147 - if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 26.148 - if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 26.149 - if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 26.150 + if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 26.151 + if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 26.152 + if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 26.153 + if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 26.154 end 26.155 12'd16: 26.156 begin 26.157 if (sel_i[0])begin 26.158 - stop_type[4:0] <= dat_i[4:0]; 26.159 + stop_type[4:0] <= #1 dat_i[4:0]; 26.160 end 26.161 end 26.162 endcase 26.163 @@ -189,27 +212,27 @@ 26.164 case ({adr_i[11:2],2'b0}) 26.165 // read the trig type 26.166 12'd0: 26.167 - reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 26.168 + reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 26.169 12'd4: 26.170 - reg_dat_o <= trace_len; 26.171 + reg_dat_o <= #1 trace_len; 26.172 12'd8: 26.173 - reg_dat_o <= pc_low; 26.174 + reg_dat_o <= #1 pc_low; 26.175 12'd12: 26.176 - reg_dat_o <= pc_high; 26.177 + reg_dat_o <= #1 pc_high; 26.178 default: 26.179 - reg_dat_o <= {27'b0,stop_type}; 26.180 + reg_dat_o <= #1 {27'b0,stop_type}; 26.181 endcase 26.182 end // else: !if(we_i == `TRUE) 26.183 end else // read / write memory 26.184 if (we_i == `FALSE) begin 26.185 - ack_o <= `TRUE; 26.186 + ack_o <= #1 `TRUE; 26.187 end else 26.188 - ack_o <= `FALSE; 26.189 + ack_o <= #1 `FALSE; 26.190 // not allowed to write to trace memory 26.191 end else begin // if (stb_i == `TRUE) 26.192 - trace_start <= `FALSE; 26.193 - trace_stop <= `FALSE; 26.194 - ack_o <= `FALSE; 26.195 + trace_start <= #1 `FALSE; 26.196 + trace_stop <= #1 `FALSE; 26.197 + ack_o <= #1 `FALSE; 26.198 end // else: !if(stb_i == `TRUE) 26.199 end // else: !if(rst_i == `TRUE) 26.200 end 26.201 @@ -245,31 +268,31 @@ 26.202 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.203 begin 26.204 if (rst_i == `TRUE) begin 26.205 - tstate <= 0; 26.206 - trace_we <= 0; 26.207 - trace_len <= 0; 26.208 - ovrflw <= `FALSE; 26.209 - mem_valid <= 0; 26.210 - started <= 0; 26.211 - capturing <= 0; 26.212 + tstate <= #1 0; 26.213 + trace_we <= #1 0; 26.214 + trace_len <= #1 0; 26.215 + ovrflw <= #1 `FALSE; 26.216 + mem_valid <= #1 0; 26.217 + started <= #1 0; 26.218 + capturing <= #1 0; 26.219 end else begin 26.220 case (tstate) 26.221 3'd0: 26.222 // start capture 26.223 if (trace_start) begin 26.224 - tstate <= 3'd1; 26.225 - mem_valid <= 0; 26.226 - started <= 1; 26.227 + tstate <= #1 3'd1; 26.228 + mem_valid <= #1 0; 26.229 + started <= #1 1; 26.230 end 26.231 3'd1: 26.232 begin 26.233 // wait for trigger 26.234 if (trace_begin) begin 26.235 - capturing <= 1; 26.236 - tstate <= 3'd2; 26.237 - trace_we <= `TRUE; 26.238 - trace_len <= 0; 26.239 - ovrflw <= `FALSE; 26.240 + capturing <= #1 1; 26.241 + tstate <= #1 3'd2; 26.242 + trace_we <= #1 `TRUE; 26.243 + trace_len <= #1 0; 26.244 + ovrflw <= #1 `FALSE; 26.245 end 26.246 end // case: 3'd1 26.247 26.248 @@ -277,18 +300,18 @@ 26.249 begin 26.250 if (trace_pc_valid) begin 26.251 if (trace_len[mem_addr_width]) 26.252 - trace_len <= 0; 26.253 + trace_len <= #1 0; 26.254 else 26.255 - trace_len <= trace_len + 1; 26.256 + trace_len <= #1 trace_len + 1; 26.257 end 26.258 - if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 26.259 + if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 26.260 // wait for stop condition 26.261 if (trace_end) begin 26.262 - tstate <= 3'd0; 26.263 - trace_we <= 0; 26.264 - mem_valid <= 1; 26.265 - started <= 0; 26.266 - capturing <= 0; 26.267 + tstate <= #1 3'd0; 26.268 + trace_we <= #1 0; 26.269 + mem_valid <= #1 1; 26.270 + started <= #1 0; 26.271 + capturing <= #1 0; 26.272 end 26.273 end // case: 3'd2 26.274 endcase
27.1 --- a/spiprog.v Sun Mar 06 21:14:43 2011 +0000 27.2 +++ b/spiprog.v Sat Aug 06 00:02:46 2011 +0100 27.3 @@ -1,18 +1,39 @@ 27.4 -// ============================================================================= 27.5 -// COPYRIGHT NOTICE 27.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 27.7 -// ALL RIGHTS RESERVED 27.8 -// This confidential and proprietary software may be used only as authorised by 27.9 -// a licensing agreement from Lattice Semiconductor Corporation. 27.10 -// The entire notice above must be reproduced on all authorized copies and 27.11 -// copies may only be made to the extent permitted by a licensing agreement from 27.12 -// Lattice Semiconductor Corporation. 27.13 +// ================================================================== 27.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 27.15 +// ------------------------------------------------------------------ 27.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 27.17 +// ALL RIGHTS RESERVED 27.18 +// ------------------------------------------------------------------ 27.19 +// 27.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 27.21 +// 27.22 +// Permission: 27.23 +// 27.24 +// Lattice Semiconductor grants permission to use this code 27.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 27.26 +// Open Source License Agreement. 27.27 +// 27.28 +// Disclaimer: 27.29 // 27.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 27.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 27.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 27.33 -// U.S.A email: techsupport@latticesemi.com 27.34 -// =============================================================================/ 27.35 +// Lattice Semiconductor provides no warranty regarding the use or 27.36 +// functionality of this code. It is the user's responsibility to 27.37 +// verify the user’s design for consistency and functionality through 27.38 +// the use of formal verification methods. 27.39 +// 27.40 +// -------------------------------------------------------------------- 27.41 +// 27.42 +// Lattice Semiconductor Corporation 27.43 +// 5555 NE Moore Court 27.44 +// Hillsboro, OR 97214 27.45 +// U.S.A 27.46 +// 27.47 +// TEL: 1-800-Lattice (USA and Canada) 27.48 +// 503-286-8001 (other locations) 27.49 +// 27.50 +// web: http://www.latticesemi.com/ 27.51 +// email: techsupport@latticesemi.com 27.52 +// 27.53 +// -------------------------------------------------------------------- 27.54 // FILE DETAILS 27.55 // Project : LatticeMico32 27.56 // File : SPIPROG.v
28.1 --- a/typea.v Sun Mar 06 21:14:43 2011 +0000 28.2 +++ b/typea.v Sat Aug 06 00:02:46 2011 +0100 28.3 @@ -1,18 +1,39 @@ 28.4 -// ============================================================================= 28.5 -// COPYRIGHT NOTICE 28.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 28.7 -// ALL RIGHTS RESERVED 28.8 -// This confidential and proprietary software may be used only as authorised by 28.9 -// a licensing agreement from Lattice Semiconductor Corporation. 28.10 -// The entire notice above must be reproduced on all authorized copies and 28.11 -// copies may only be made to the extent permitted by a licensing agreement from 28.12 -// Lattice Semiconductor Corporation. 28.13 +// ================================================================== 28.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 28.15 +// ------------------------------------------------------------------ 28.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 28.17 +// ALL RIGHTS RESERVED 28.18 +// ------------------------------------------------------------------ 28.19 +// 28.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 28.21 +// 28.22 +// Permission: 28.23 +// 28.24 +// Lattice Semiconductor grants permission to use this code 28.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 28.26 +// Open Source License Agreement. 28.27 +// 28.28 +// Disclaimer: 28.29 // 28.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 28.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 28.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 28.33 -// U.S.A email: techsupport@latticesemi.com 28.34 -// =============================================================================/ 28.35 +// Lattice Semiconductor provides no warranty regarding the use or 28.36 +// functionality of this code. It is the user's responsibility to 28.37 +// verify the user’s design for consistency and functionality through 28.38 +// the use of formal verification methods. 28.39 +// 28.40 +// -------------------------------------------------------------------- 28.41 +// 28.42 +// Lattice Semiconductor Corporation 28.43 +// 5555 NE Moore Court 28.44 +// Hillsboro, OR 97214 28.45 +// U.S.A 28.46 +// 28.47 +// TEL: 1-800-Lattice (USA and Canada) 28.48 +// 503-286-8001 (other locations) 28.49 +// 28.50 +// web: http://www.latticesemi.com/ 28.51 +// email: techsupport@latticesemi.com 28.52 +// 28.53 +// -------------------------------------------------------------------- 28.54 // FILE DETAILS 28.55 // Project : LatticeMico32 28.56 // File : TYPEA.v 28.57 @@ -59,13 +80,13 @@ 28.58 always @ (negedge CLK or negedge RESET_N) 28.59 begin 28.60 if (RESET_N == 1'b0) 28.61 - tdoInt <= 1'b0; 28.62 + tdoInt <= #1 1'b0; 28.63 else if (CLK == 1'b0) 28.64 if (CLKEN == 1'b1) 28.65 if (CAPTURE_DR == 1'b0) 28.66 - tdoInt <= TDI; 28.67 + tdoInt <= #1 TDI; 28.68 else 28.69 - tdoInt <= DATA_IN; 28.70 + tdoInt <= #1 DATA_IN; 28.71 end 28.72 28.73 assign TDO = tdoInt; 28.74 @@ -73,9 +94,9 @@ 28.75 always @ (negedge CLK or negedge RESET_N) 28.76 begin 28.77 if (RESET_N == 1'b0) 28.78 - DATA_OUT <= 1'b0; 28.79 + DATA_OUT <= #1 1'b0; 28.80 else if (CLK == 1'b0) 28.81 if (UPDATE_DR == 1'b1) 28.82 - DATA_OUT <= tdoInt; 28.83 + DATA_OUT <= #1 tdoInt; 28.84 end 28.85 endmodule
29.1 --- a/typeb.v Sun Mar 06 21:14:43 2011 +0000 29.2 +++ b/typeb.v Sat Aug 06 00:02:46 2011 +0100 29.3 @@ -1,18 +1,39 @@ 29.4 -// ============================================================================= 29.5 -// COPYRIGHT NOTICE 29.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 29.7 -// ALL RIGHTS RESERVED 29.8 -// This confidential and proprietary software may be used only as authorised by 29.9 -// a licensing agreement from Lattice Semiconductor Corporation. 29.10 -// The entire notice above must be reproduced on all authorized copies and 29.11 -// copies may only be made to the extent permitted by a licensing agreement from 29.12 -// Lattice Semiconductor Corporation. 29.13 +// ================================================================== 29.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 29.15 +// ------------------------------------------------------------------ 29.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 29.17 +// ALL RIGHTS RESERVED 29.18 +// ------------------------------------------------------------------ 29.19 +// 29.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 29.21 +// 29.22 +// Permission: 29.23 +// 29.24 +// Lattice Semiconductor grants permission to use this code 29.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 29.26 +// Open Source License Agreement. 29.27 +// 29.28 +// Disclaimer: 29.29 // 29.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 29.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 29.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 29.33 -// U.S.A email: techsupport@latticesemi.com 29.34 -// =============================================================================/ 29.35 +// Lattice Semiconductor provides no warranty regarding the use or 29.36 +// functionality of this code. It is the user's responsibility to 29.37 +// verify the user’s design for consistency and functionality through 29.38 +// the use of formal verification methods. 29.39 +// 29.40 +// -------------------------------------------------------------------- 29.41 +// 29.42 +// Lattice Semiconductor Corporation 29.43 +// 5555 NE Moore Court 29.44 +// Hillsboro, OR 97214 29.45 +// U.S.A 29.46 +// 29.47 +// TEL: 1-800-Lattice (USA and Canada) 29.48 +// 503-286-8001 (other locations) 29.49 +// 29.50 +// web: http://www.latticesemi.com/ 29.51 +// email: techsupport@latticesemi.com 29.52 +// 29.53 +// -------------------------------------------------------------------- 29.54 // FILE DETAILS 29.55 // Project : LatticeMico32 29.56 // File : TYPEB.v 29.57 @@ -43,13 +64,13 @@ 29.58 always @ (negedge CLK or negedge RESET_N) 29.59 begin 29.60 if (RESET_N== 1'b0) 29.61 - tdoInt <= 1'b0; 29.62 + tdoInt <= #1 1'b0; 29.63 else if (CLK == 1'b0) 29.64 if (CLKEN==1'b1) 29.65 if (CAPTURE_DR==1'b0) 29.66 - tdoInt <= TDI; 29.67 + tdoInt <= #1 TDI; 29.68 else 29.69 - tdoInt <= DATA_IN; 29.70 + tdoInt <= #1 DATA_IN; 29.71 end 29.72 29.73 assign TDO = tdoInt;