Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
| lm32_cpu.v | file | annotate | diff | revisions | |
| lm32_dcache.v | file | annotate | diff | revisions | |
| lm32_debug.v | file | annotate | diff | revisions | |
| lm32_icache.v | file | annotate | diff | revisions | |
| lm32_instruction_unit.v | file | annotate | diff | revisions | |
| lm32_interrupt.v | file | annotate | diff | revisions | |
| lm32_jtag.v | file | annotate | diff | revisions | |
| lm32_load_store_unit.v | file | annotate | diff | revisions | |
| lm32_mc_arithmetic.v | file | annotate | diff | revisions | |
| lm32_monitor.v | file | annotate | diff | revisions | |
| lm32_multiplier.v | file | annotate | diff | revisions | |
| lm32_ram.v | file | annotate | diff | revisions | |
| lm32_shifter.v | file | annotate | diff | revisions | |
| lm32_trace.v | file | annotate | diff | revisions | |
| typea.v | file | annotate | diff | revisions | |
| typeb.v | file | annotate | diff | revisions |
1.1 --- a/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 1.2 +++ b/lm32_cpu.v Sat Aug 06 01:26:56 2011 +0100 1.3 @@ -1298,15 +1298,15 @@ 1.4 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.5 if (rst_i == `TRUE) 1.6 begin 1.7 - regfile_raw_0 <= #1 1'b0; 1.8 - regfile_raw_1 <= #1 1'b0; 1.9 - w_result_d <= #1 32'b0; 1.10 + regfile_raw_0 <= 1'b0; 1.11 + regfile_raw_1 <= 1'b0; 1.12 + w_result_d <= 32'b0; 1.13 end 1.14 else 1.15 begin 1.16 - regfile_raw_0 <= #1 regfile_raw_0_nxt; 1.17 - regfile_raw_1 <= #1 regfile_raw_1_nxt; 1.18 - w_result_d <= #1 w_result; 1.19 + regfile_raw_0 <= regfile_raw_0_nxt; 1.20 + regfile_raw_1 <= regfile_raw_1_nxt; 1.21 + w_result_d <= w_result; 1.22 end 1.23 1.24 /*---------------------------------------------------------------------- 1.25 @@ -2132,14 +2132,14 @@ 1.26 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.27 begin 1.28 if (rst_i == `TRUE) 1.29 - eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.30 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.31 else 1.32 begin 1.33 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 1.34 - eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.35 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.36 `ifdef CFG_HW_DEBUG_ENABLED 1.37 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 1.38 - eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.39 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.40 `endif 1.41 end 1.42 end 1.43 @@ -2149,14 +2149,14 @@ 1.44 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.45 begin 1.46 if (rst_i == `TRUE) 1.47 - deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.48 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.49 else 1.50 begin 1.51 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 1.52 - deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.53 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.54 `ifdef CFG_HW_DEBUG_ENABLED 1.55 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 1.56 - deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.57 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.58 `endif 1.59 end 1.60 end 1.61 @@ -2167,9 +2167,9 @@ 1.62 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.63 begin 1.64 if (rst_i == `TRUE) 1.65 - cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.66 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 1.67 else 1.68 - cc <= #1 cc + 1'b1; 1.69 + cc <= cc + 1'b1; 1.70 end 1.71 `endif 1.72 1.73 @@ -2178,15 +2178,15 @@ 1.74 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.75 begin 1.76 if (rst_i == `TRUE) 1.77 - data_bus_error_seen <= #1 `FALSE; 1.78 + data_bus_error_seen <= `FALSE; 1.79 else 1.80 begin 1.81 // Set flag when bus error is detected 1.82 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 1.83 - data_bus_error_seen <= #1 `TRUE; 1.84 + data_bus_error_seen <= `TRUE; 1.85 // Clear flag when exception is taken 1.86 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 1.87 - data_bus_error_seen <= #1 `FALSE; 1.88 + data_bus_error_seen <= `FALSE; 1.89 end 1.90 end 1.91 `endif 1.92 @@ -2237,48 +2237,48 @@ 1.93 begin 1.94 if (rst_i == `TRUE) 1.95 begin 1.96 - valid_f <= #1 `FALSE; 1.97 - valid_d <= #1 `FALSE; 1.98 - valid_x <= #1 `FALSE; 1.99 - valid_m <= #1 `FALSE; 1.100 - valid_w <= #1 `FALSE; 1.101 + valid_f <= `FALSE; 1.102 + valid_d <= `FALSE; 1.103 + valid_x <= `FALSE; 1.104 + valid_m <= `FALSE; 1.105 + valid_w <= `FALSE; 1.106 end 1.107 else 1.108 begin 1.109 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 1.110 `ifdef LM32_CACHE_ENABLED 1.111 - valid_f <= #1 valid_a; 1.112 + valid_f <= valid_a; 1.113 `else 1.114 - valid_f <= #1 `TRUE; 1.115 + valid_f <= `TRUE; 1.116 `endif 1.117 else if (stall_f == `FALSE) 1.118 - valid_f <= #1 `FALSE; 1.119 + valid_f <= `FALSE; 1.120 1.121 if (kill_d == `TRUE) 1.122 - valid_d <= #1 `FALSE; 1.123 + valid_d <= `FALSE; 1.124 else if (stall_f == `FALSE) 1.125 - valid_d <= #1 valid_f & !kill_f; 1.126 + valid_d <= valid_f & !kill_f; 1.127 else if (stall_d == `FALSE) 1.128 - valid_d <= #1 `FALSE; 1.129 + valid_d <= `FALSE; 1.130 1.131 if (stall_d == `FALSE) 1.132 - valid_x <= #1 valid_d & !kill_d; 1.133 + valid_x <= valid_d & !kill_d; 1.134 else if (kill_x == `TRUE) 1.135 - valid_x <= #1 `FALSE; 1.136 + valid_x <= `FALSE; 1.137 else if (stall_x == `FALSE) 1.138 - valid_x <= #1 `FALSE; 1.139 + valid_x <= `FALSE; 1.140 1.141 if (kill_m == `TRUE) 1.142 - valid_m <= #1 `FALSE; 1.143 + valid_m <= `FALSE; 1.144 else if (stall_x == `FALSE) 1.145 - valid_m <= #1 valid_x & !kill_x; 1.146 + valid_m <= valid_x & !kill_x; 1.147 else if (stall_m == `FALSE) 1.148 - valid_m <= #1 `FALSE; 1.149 + valid_m <= `FALSE; 1.150 1.151 if (stall_m == `FALSE) 1.152 - valid_w <= #1 valid_m & !kill_m; 1.153 + valid_w <= valid_m & !kill_m; 1.154 else 1.155 - valid_w <= #1 `FALSE; 1.156 + valid_w <= `FALSE; 1.157 end 1.158 end 1.159 1.160 @@ -2288,113 +2288,113 @@ 1.161 if (rst_i == `TRUE) 1.162 begin 1.163 `ifdef CFG_USER_ENABLED 1.164 - user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.165 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.166 `endif 1.167 - operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.168 - operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.169 - store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.170 - branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.171 - x_result_sel_csr_x <= #1 `FALSE; 1.172 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.173 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.174 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.175 + branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.176 + x_result_sel_csr_x <= `FALSE; 1.177 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.178 - x_result_sel_mc_arith_x <= #1 `FALSE; 1.179 + x_result_sel_mc_arith_x <= `FALSE; 1.180 `endif 1.181 `ifdef LM32_NO_BARREL_SHIFT 1.182 - x_result_sel_shift_x <= #1 `FALSE; 1.183 + x_result_sel_shift_x <= `FALSE; 1.184 `endif 1.185 `ifdef CFG_SIGN_EXTEND_ENABLED 1.186 - x_result_sel_sext_x <= #1 `FALSE; 1.187 + x_result_sel_sext_x <= `FALSE; 1.188 `endif 1.189 - x_result_sel_logic_x <= #1 `FALSE; 1.190 + x_result_sel_logic_x <= `FALSE; 1.191 `ifdef CFG_USER_ENABLED 1.192 - x_result_sel_user_x <= #1 `FALSE; 1.193 + x_result_sel_user_x <= `FALSE; 1.194 `endif 1.195 - x_result_sel_add_x <= #1 `FALSE; 1.196 - m_result_sel_compare_x <= #1 `FALSE; 1.197 + x_result_sel_add_x <= `FALSE; 1.198 + m_result_sel_compare_x <= `FALSE; 1.199 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.200 - m_result_sel_shift_x <= #1 `FALSE; 1.201 + m_result_sel_shift_x <= `FALSE; 1.202 `endif 1.203 - w_result_sel_load_x <= #1 `FALSE; 1.204 + w_result_sel_load_x <= `FALSE; 1.205 `ifdef CFG_PL_MULTIPLY_ENABLED 1.206 - w_result_sel_mul_x <= #1 `FALSE; 1.207 + w_result_sel_mul_x <= `FALSE; 1.208 `endif 1.209 - x_bypass_enable_x <= #1 `FALSE; 1.210 - m_bypass_enable_x <= #1 `FALSE; 1.211 - write_enable_x <= #1 `FALSE; 1.212 - write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.213 - csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 1.214 - load_x <= #1 `FALSE; 1.215 - store_x <= #1 `FALSE; 1.216 - size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 1.217 - sign_extend_x <= #1 `FALSE; 1.218 - adder_op_x <= #1 `FALSE; 1.219 - adder_op_x_n <= #1 `FALSE; 1.220 - logic_op_x <= #1 4'h0; 1.221 + x_bypass_enable_x <= `FALSE; 1.222 + m_bypass_enable_x <= `FALSE; 1.223 + write_enable_x <= `FALSE; 1.224 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.225 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 1.226 + load_x <= `FALSE; 1.227 + store_x <= `FALSE; 1.228 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 1.229 + sign_extend_x <= `FALSE; 1.230 + adder_op_x <= `FALSE; 1.231 + adder_op_x_n <= `FALSE; 1.232 + logic_op_x <= 4'h0; 1.233 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.234 - direction_x <= #1 `FALSE; 1.235 + direction_x <= `FALSE; 1.236 `endif 1.237 `ifdef CFG_ROTATE_ENABLED 1.238 - rotate_x <= #1 `FALSE; 1.239 + rotate_x <= `FALSE; 1.240 1.241 `endif 1.242 - branch_x <= #1 `FALSE; 1.243 - branch_predict_x <= #1 `FALSE; 1.244 - branch_predict_taken_x <= #1 `FALSE; 1.245 - condition_x <= #1 `LM32_CONDITION_U1; 1.246 + branch_x <= `FALSE; 1.247 + branch_predict_x <= `FALSE; 1.248 + branch_predict_taken_x <= `FALSE; 1.249 + condition_x <= `LM32_CONDITION_U1; 1.250 `ifdef CFG_DEBUG_ENABLED 1.251 - break_x <= #1 `FALSE; 1.252 + break_x <= `FALSE; 1.253 `endif 1.254 - scall_x <= #1 `FALSE; 1.255 - eret_x <= #1 `FALSE; 1.256 + scall_x <= `FALSE; 1.257 + eret_x <= `FALSE; 1.258 `ifdef CFG_DEBUG_ENABLED 1.259 - bret_x <= #1 `FALSE; 1.260 + bret_x <= `FALSE; 1.261 `endif 1.262 `ifdef CFG_BUS_ERRORS_ENABLED 1.263 - bus_error_x <= #1 `FALSE; 1.264 - data_bus_error_exception_m <= #1 `FALSE; 1.265 + bus_error_x <= `FALSE; 1.266 + data_bus_error_exception_m <= `FALSE; 1.267 `endif 1.268 - csr_write_enable_x <= #1 `FALSE; 1.269 - operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.270 - branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.271 - m_result_sel_compare_m <= #1 `FALSE; 1.272 + csr_write_enable_x <= `FALSE; 1.273 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.274 + branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.275 + m_result_sel_compare_m <= `FALSE; 1.276 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.277 - m_result_sel_shift_m <= #1 `FALSE; 1.278 + m_result_sel_shift_m <= `FALSE; 1.279 `endif 1.280 - w_result_sel_load_m <= #1 `FALSE; 1.281 + w_result_sel_load_m <= `FALSE; 1.282 `ifdef CFG_PL_MULTIPLY_ENABLED 1.283 - w_result_sel_mul_m <= #1 `FALSE; 1.284 + w_result_sel_mul_m <= `FALSE; 1.285 `endif 1.286 - m_bypass_enable_m <= #1 `FALSE; 1.287 - branch_m <= #1 `FALSE; 1.288 - branch_predict_m <= #1 `FALSE; 1.289 - branch_predict_taken_m <= #1 `FALSE; 1.290 - exception_m <= #1 `FALSE; 1.291 - load_m <= #1 `FALSE; 1.292 - store_m <= #1 `FALSE; 1.293 - write_enable_m <= #1 `FALSE; 1.294 - write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.295 - condition_met_m <= #1 `FALSE; 1.296 + m_bypass_enable_m <= `FALSE; 1.297 + branch_m <= `FALSE; 1.298 + branch_predict_m <= `FALSE; 1.299 + branch_predict_taken_m <= `FALSE; 1.300 + exception_m <= `FALSE; 1.301 + load_m <= `FALSE; 1.302 + store_m <= `FALSE; 1.303 + write_enable_m <= `FALSE; 1.304 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.305 + condition_met_m <= `FALSE; 1.306 `ifdef CFG_DCACHE_ENABLED 1.307 - dflush_m <= #1 `FALSE; 1.308 + dflush_m <= `FALSE; 1.309 `endif 1.310 `ifdef CFG_DEBUG_ENABLED 1.311 - debug_exception_m <= #1 `FALSE; 1.312 - non_debug_exception_m <= #1 `FALSE; 1.313 + debug_exception_m <= `FALSE; 1.314 + non_debug_exception_m <= `FALSE; 1.315 `endif 1.316 - operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.317 - w_result_sel_load_w <= #1 `FALSE; 1.318 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.319 + w_result_sel_load_w <= `FALSE; 1.320 `ifdef CFG_PL_MULTIPLY_ENABLED 1.321 - w_result_sel_mul_w <= #1 `FALSE; 1.322 + w_result_sel_mul_w <= `FALSE; 1.323 `endif 1.324 - write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.325 - write_enable_w <= #1 `FALSE; 1.326 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.327 + write_enable_w <= `FALSE; 1.328 `ifdef CFG_DEBUG_ENABLED 1.329 - debug_exception_w <= #1 `FALSE; 1.330 - non_debug_exception_w <= #1 `FALSE; 1.331 + debug_exception_w <= `FALSE; 1.332 + non_debug_exception_w <= `FALSE; 1.333 `else 1.334 - exception_w <= #1 `FALSE; 1.335 + exception_w <= `FALSE; 1.336 `endif 1.337 `ifdef CFG_BUS_ERRORS_ENABLED 1.338 - memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.339 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.340 `endif 1.341 end 1.342 else 1.343 @@ -2404,105 +2404,105 @@ 1.344 if (stall_x == `FALSE) 1.345 begin 1.346 `ifdef CFG_USER_ENABLED 1.347 - user_opcode <= #1 user_opcode_d; 1.348 + user_opcode <= user_opcode_d; 1.349 `endif 1.350 - operand_0_x <= #1 d_result_0; 1.351 - operand_1_x <= #1 d_result_1; 1.352 - store_operand_x <= #1 bypass_data_1; 1.353 - branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.354 - x_result_sel_csr_x <= #1 x_result_sel_csr_d; 1.355 + operand_0_x <= d_result_0; 1.356 + operand_1_x <= d_result_1; 1.357 + store_operand_x <= bypass_data_1; 1.358 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.359 + x_result_sel_csr_x <= x_result_sel_csr_d; 1.360 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.361 - x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 1.362 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 1.363 `endif 1.364 `ifdef LM32_NO_BARREL_SHIFT 1.365 - x_result_sel_shift_x <= #1 x_result_sel_shift_d; 1.366 + x_result_sel_shift_x <= x_result_sel_shift_d; 1.367 `endif 1.368 `ifdef CFG_SIGN_EXTEND_ENABLED 1.369 - x_result_sel_sext_x <= #1 x_result_sel_sext_d; 1.370 + x_result_sel_sext_x <= x_result_sel_sext_d; 1.371 `endif 1.372 - x_result_sel_logic_x <= #1 x_result_sel_logic_d; 1.373 + x_result_sel_logic_x <= x_result_sel_logic_d; 1.374 `ifdef CFG_USER_ENABLED 1.375 - x_result_sel_user_x <= #1 x_result_sel_user_d; 1.376 + x_result_sel_user_x <= x_result_sel_user_d; 1.377 `endif 1.378 - x_result_sel_add_x <= #1 x_result_sel_add_d; 1.379 - m_result_sel_compare_x <= #1 m_result_sel_compare_d; 1.380 + x_result_sel_add_x <= x_result_sel_add_d; 1.381 + m_result_sel_compare_x <= m_result_sel_compare_d; 1.382 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.383 - m_result_sel_shift_x <= #1 m_result_sel_shift_d; 1.384 + m_result_sel_shift_x <= m_result_sel_shift_d; 1.385 `endif 1.386 - w_result_sel_load_x <= #1 w_result_sel_load_d; 1.387 + w_result_sel_load_x <= w_result_sel_load_d; 1.388 `ifdef CFG_PL_MULTIPLY_ENABLED 1.389 - w_result_sel_mul_x <= #1 w_result_sel_mul_d; 1.390 + w_result_sel_mul_x <= w_result_sel_mul_d; 1.391 `endif 1.392 - x_bypass_enable_x <= #1 x_bypass_enable_d; 1.393 - m_bypass_enable_x <= #1 m_bypass_enable_d; 1.394 - load_x <= #1 load_d; 1.395 - store_x <= #1 store_d; 1.396 - branch_x <= #1 branch_d; 1.397 - branch_predict_x <= #1 branch_predict_d; 1.398 - branch_predict_taken_x <= #1 branch_predict_taken_d; 1.399 - write_idx_x <= #1 write_idx_d; 1.400 - csr_x <= #1 csr_d; 1.401 - size_x <= #1 size_d; 1.402 - sign_extend_x <= #1 sign_extend_d; 1.403 - adder_op_x <= #1 adder_op_d; 1.404 - adder_op_x_n <= #1 ~adder_op_d; 1.405 - logic_op_x <= #1 logic_op_d; 1.406 + x_bypass_enable_x <= x_bypass_enable_d; 1.407 + m_bypass_enable_x <= m_bypass_enable_d; 1.408 + load_x <= load_d; 1.409 + store_x <= store_d; 1.410 + branch_x <= branch_d; 1.411 + branch_predict_x <= branch_predict_d; 1.412 + branch_predict_taken_x <= branch_predict_taken_d; 1.413 + write_idx_x <= write_idx_d; 1.414 + csr_x <= csr_d; 1.415 + size_x <= size_d; 1.416 + sign_extend_x <= sign_extend_d; 1.417 + adder_op_x <= adder_op_d; 1.418 + adder_op_x_n <= ~adder_op_d; 1.419 + logic_op_x <= logic_op_d; 1.420 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.421 - direction_x <= #1 direction_d; 1.422 + direction_x <= direction_d; 1.423 `endif 1.424 `ifdef CFG_ROTATE_ENABLED 1.425 - rotate_x <= #1 rotate_d; 1.426 + rotate_x <= rotate_d; 1.427 `endif 1.428 - condition_x <= #1 condition_d; 1.429 - csr_write_enable_x <= #1 csr_write_enable_d; 1.430 + condition_x <= condition_d; 1.431 + csr_write_enable_x <= csr_write_enable_d; 1.432 `ifdef CFG_DEBUG_ENABLED 1.433 - break_x <= #1 break_d; 1.434 + break_x <= break_d; 1.435 `endif 1.436 - scall_x <= #1 scall_d; 1.437 + scall_x <= scall_d; 1.438 `ifdef CFG_BUS_ERRORS_ENABLED 1.439 - bus_error_x <= #1 bus_error_d; 1.440 + bus_error_x <= bus_error_d; 1.441 `endif 1.442 - eret_x <= #1 eret_d; 1.443 + eret_x <= eret_d; 1.444 `ifdef CFG_DEBUG_ENABLED 1.445 - bret_x <= #1 bret_d; 1.446 + bret_x <= bret_d; 1.447 `endif 1.448 - write_enable_x <= #1 write_enable_d; 1.449 + write_enable_x <= write_enable_d; 1.450 end 1.451 1.452 // X/M stage registers 1.453 1.454 if (stall_m == `FALSE) 1.455 begin 1.456 - operand_m <= #1 x_result; 1.457 - m_result_sel_compare_m <= #1 m_result_sel_compare_x; 1.458 + operand_m <= x_result; 1.459 + m_result_sel_compare_m <= m_result_sel_compare_x; 1.460 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.461 - m_result_sel_shift_m <= #1 m_result_sel_shift_x; 1.462 + m_result_sel_shift_m <= m_result_sel_shift_x; 1.463 `endif 1.464 if (exception_x == `TRUE) 1.465 begin 1.466 - w_result_sel_load_m <= #1 `FALSE; 1.467 + w_result_sel_load_m <= `FALSE; 1.468 `ifdef CFG_PL_MULTIPLY_ENABLED 1.469 - w_result_sel_mul_m <= #1 `FALSE; 1.470 + w_result_sel_mul_m <= `FALSE; 1.471 `endif 1.472 end 1.473 else 1.474 begin 1.475 - w_result_sel_load_m <= #1 w_result_sel_load_x; 1.476 + w_result_sel_load_m <= w_result_sel_load_x; 1.477 `ifdef CFG_PL_MULTIPLY_ENABLED 1.478 - w_result_sel_mul_m <= #1 w_result_sel_mul_x; 1.479 + w_result_sel_mul_m <= w_result_sel_mul_x; 1.480 `endif 1.481 end 1.482 - m_bypass_enable_m <= #1 m_bypass_enable_x; 1.483 + m_bypass_enable_m <= m_bypass_enable_x; 1.484 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.485 `endif 1.486 - load_m <= #1 load_x; 1.487 - store_m <= #1 store_x; 1.488 + load_m <= load_x; 1.489 + store_m <= store_x; 1.490 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.491 - branch_m <= #1 branch_x && !branch_taken_x; 1.492 + branch_m <= branch_x && !branch_taken_x; 1.493 `else 1.494 - branch_m <= #1 branch_x; 1.495 - branch_predict_m <= #1 branch_predict_x; 1.496 - branch_predict_taken_m <= #1 branch_predict_taken_x; 1.497 + branch_m <= branch_x; 1.498 + branch_predict_m <= branch_predict_x; 1.499 + branch_predict_taken_m <= branch_predict_taken_x; 1.500 `endif 1.501 `ifdef CFG_DEBUG_ENABLED 1.502 // Data bus errors are generated by the wishbone and are 1.503 @@ -2511,18 +2511,18 @@ 1.504 // in same cycle (causing a debug exception). Handle non 1.505 // -debug exception first! 1.506 if (non_debug_exception_x == `TRUE) 1.507 - write_idx_m <= #1 `LM32_EA_REG; 1.508 + write_idx_m <= `LM32_EA_REG; 1.509 else if (debug_exception_x == `TRUE) 1.510 - write_idx_m <= #1 `LM32_BA_REG; 1.511 + write_idx_m <= `LM32_BA_REG; 1.512 else 1.513 - write_idx_m <= #1 write_idx_x; 1.514 + write_idx_m <= write_idx_x; 1.515 `else 1.516 if (exception_x == `TRUE) 1.517 - write_idx_m <= #1 `LM32_EA_REG; 1.518 + write_idx_m <= `LM32_EA_REG; 1.519 else 1.520 - write_idx_m <= #1 write_idx_x; 1.521 + write_idx_m <= write_idx_x; 1.522 `endif 1.523 - condition_met_m <= #1 condition_met_x; 1.524 + condition_met_m <= condition_met_x; 1.525 `ifdef CFG_DEBUG_ENABLED 1.526 if (exception_x == `TRUE) 1.527 if ((dc_re == `TRUE) 1.528 @@ -2531,28 +2531,28 @@ 1.529 `endif 1.530 || ((debug_exception_x == `TRUE) 1.531 && (non_debug_exception_x == `FALSE))) 1.532 - branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 1.533 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.534 else 1.535 - branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 1.536 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 1.537 else 1.538 - branch_target_m <= #1 branch_target_x; 1.539 + branch_target_m <= branch_target_x; 1.540 `else 1.541 - branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.542 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.543 `endif 1.544 `ifdef CFG_TRACE_ENABLED 1.545 - eid_m <= #1 eid_x; 1.546 + eid_m <= eid_x; 1.547 `endif 1.548 `ifdef CFG_DCACHE_ENABLED 1.549 - dflush_m <= #1 dflush_x; 1.550 + dflush_m <= dflush_x; 1.551 `endif 1.552 - eret_m <= #1 eret_q_x; 1.553 + eret_m <= eret_q_x; 1.554 `ifdef CFG_DEBUG_ENABLED 1.555 - bret_m <= #1 bret_q_x; 1.556 + bret_m <= bret_q_x; 1.557 `endif 1.558 - write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 1.559 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 1.560 `ifdef CFG_DEBUG_ENABLED 1.561 - debug_exception_m <= #1 debug_exception_x; 1.562 - non_debug_exception_m <= #1 non_debug_exception_x; 1.563 + debug_exception_m <= debug_exception_x; 1.564 + non_debug_exception_m <= non_debug_exception_x; 1.565 `endif 1.566 end 1.567 1.568 @@ -2560,11 +2560,11 @@ 1.569 if (stall_m == `FALSE) 1.570 begin 1.571 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.572 - exception_m <= #1 `TRUE; 1.573 + exception_m <= `TRUE; 1.574 else 1.575 - exception_m <= #1 `FALSE; 1.576 + exception_m <= `FALSE; 1.577 `ifdef CFG_BUS_ERRORS_ENABLED 1.578 - data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 1.579 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 1.580 `ifdef CFG_DEBUG_ENABLED 1.581 && (reset_exception == `FALSE) 1.582 `endif 1.583 @@ -2574,28 +2574,28 @@ 1.584 1.585 // M/W stage registers 1.586 `ifdef CFG_BUS_ERRORS_ENABLED 1.587 - operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.588 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.589 `else 1.590 - operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.591 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.592 `endif 1.593 - w_result_sel_load_w <= #1 w_result_sel_load_m; 1.594 + w_result_sel_load_w <= w_result_sel_load_m; 1.595 `ifdef CFG_PL_MULTIPLY_ENABLED 1.596 - w_result_sel_mul_w <= #1 w_result_sel_mul_m; 1.597 + w_result_sel_mul_w <= w_result_sel_mul_m; 1.598 `endif 1.599 - write_idx_w <= #1 write_idx_m; 1.600 + write_idx_w <= write_idx_m; 1.601 `ifdef CFG_TRACE_ENABLED 1.602 - eid_w <= #1 eid_m; 1.603 - eret_w <= #1 eret_m; 1.604 + eid_w <= eid_m; 1.605 + eret_w <= eret_m; 1.606 `ifdef CFG_DEBUG_ENABLED 1.607 - bret_w <= #1 bret_m; 1.608 + bret_w <= bret_m; 1.609 `endif 1.610 `endif 1.611 - write_enable_w <= #1 write_enable_m; 1.612 + write_enable_w <= write_enable_m; 1.613 `ifdef CFG_DEBUG_ENABLED 1.614 - debug_exception_w <= #1 debug_exception_m; 1.615 - non_debug_exception_w <= #1 non_debug_exception_m; 1.616 + debug_exception_w <= debug_exception_m; 1.617 + non_debug_exception_w <= non_debug_exception_m; 1.618 `else 1.619 - exception_w <= #1 exception_m; 1.620 + exception_w <= exception_m; 1.621 `endif 1.622 `ifdef CFG_BUS_ERRORS_ENABLED 1.623 if ( (stall_m == `FALSE) 1.624 @@ -2604,7 +2604,7 @@ 1.625 || (store_q_m == `TRUE) 1.626 ) 1.627 ) 1.628 - memop_pc_w <= #1 pc_m; 1.629 + memop_pc_w <= pc_m; 1.630 `endif 1.631 end 1.632 end 1.633 @@ -2616,26 +2616,26 @@ 1.634 begin 1.635 if (rst_i == `TRUE) 1.636 begin 1.637 - use_buf <= #1 `FALSE; 1.638 - reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.639 - reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.640 + use_buf <= `FALSE; 1.641 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 1.642 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 1.643 end 1.644 else 1.645 begin 1.646 if (stall_d == `FALSE) 1.647 - use_buf <= #1 `FALSE; 1.648 + use_buf <= `FALSE; 1.649 else if (use_buf == `FALSE) 1.650 begin 1.651 - reg_data_buf_0 <= #1 reg_data_live_0; 1.652 - reg_data_buf_1 <= #1 reg_data_live_1; 1.653 - use_buf <= #1 `TRUE; 1.654 + reg_data_buf_0 <= reg_data_live_0; 1.655 + reg_data_buf_1 <= reg_data_live_1; 1.656 + use_buf <= `TRUE; 1.657 end 1.658 if (reg_write_enable_q_w == `TRUE) 1.659 begin 1.660 if (write_idx_w == read_idx_0_d) 1.661 - reg_data_buf_0 <= #1 w_result; 1.662 + reg_data_buf_0 <= w_result; 1.663 if (write_idx_w == read_idx_1_d) 1.664 - reg_data_buf_1 <= #1 w_result; 1.665 + reg_data_buf_1 <= w_result; 1.666 end 1.667 end 1.668 end 1.669 @@ -2647,42 +2647,42 @@ 1.670 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.671 begin 1.672 if (rst_i == `TRUE) begin 1.673 - registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.674 - registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.675 - registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.676 - registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.677 - registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.678 - registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.679 - registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.680 - registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.681 - registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.682 - registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.683 - registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.684 - registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.685 - registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.686 - registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.687 - registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.688 - registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.689 - registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.690 - registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.691 - registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.692 - registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.693 - registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.694 - registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.695 - registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.696 - registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.697 - registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.698 - registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.699 - registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.700 - registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.701 - registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.702 - registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.703 - registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.704 - registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.705 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 1.706 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 1.707 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 1.708 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 1.709 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 1.710 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 1.711 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 1.712 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 1.713 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 1.714 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 1.715 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 1.716 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 1.717 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 1.718 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 1.719 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 1.720 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 1.721 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 1.722 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 1.723 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 1.724 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 1.725 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 1.726 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 1.727 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 1.728 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 1.729 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 1.730 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 1.731 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 1.732 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 1.733 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 1.734 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 1.735 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 1.736 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 1.737 end 1.738 else begin 1.739 if (reg_write_enable_q_w == `TRUE) 1.740 - registers[write_idx_w] <= #1 w_result; 1.741 + registers[write_idx_w] <= w_result; 1.742 end 1.743 end 1.744 `endif 1.745 @@ -2693,19 +2693,19 @@ 1.746 begin 1.747 if (rst_i == `TRUE) 1.748 begin 1.749 - trace_pc_valid <= #1 `FALSE; 1.750 - trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.751 - trace_exception <= #1 `FALSE; 1.752 - trace_eid <= #1 `LM32_EID_RESET; 1.753 - trace_eret <= #1 `FALSE; 1.754 + trace_pc_valid <= `FALSE; 1.755 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 1.756 + trace_exception <= `FALSE; 1.757 + trace_eid <= `LM32_EID_RESET; 1.758 + trace_eret <= `FALSE; 1.759 `ifdef CFG_DEBUG_ENABLED 1.760 - trace_bret <= #1 `FALSE; 1.761 + trace_bret <= `FALSE; 1.762 `endif 1.763 - pc_c <= #1 `CFG_EBA_RESET/4; 1.764 + pc_c <= `CFG_EBA_RESET/4; 1.765 end 1.766 else 1.767 begin 1.768 - trace_pc_valid <= #1 `FALSE; 1.769 + trace_pc_valid <= `FALSE; 1.770 // Has an exception occured 1.771 `ifdef CFG_DEBUG_ENABLED 1.772 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 1.773 @@ -2713,13 +2713,13 @@ 1.774 if (exception_q_w == `TRUE) 1.775 `endif 1.776 begin 1.777 - trace_exception <= #1 `TRUE; 1.778 - trace_pc_valid <= #1 `TRUE; 1.779 - trace_pc <= #1 pc_w; 1.780 - trace_eid <= #1 eid_w; 1.781 + trace_exception <= `TRUE; 1.782 + trace_pc_valid <= `TRUE; 1.783 + trace_pc <= pc_w; 1.784 + trace_eid <= eid_w; 1.785 end 1.786 else 1.787 - trace_exception <= #1 `FALSE; 1.788 + trace_exception <= `FALSE; 1.789 1.790 if ((valid_w == `TRUE) && (!kill_w)) 1.791 begin 1.792 @@ -2727,22 +2727,22 @@ 1.793 if (pc_c + 1'b1 != pc_w) 1.794 begin 1.795 // Non-sequential instruction 1.796 - trace_pc_valid <= #1 `TRUE; 1.797 - trace_pc <= #1 pc_w; 1.798 + trace_pc_valid <= `TRUE; 1.799 + trace_pc <= pc_w; 1.800 end 1.801 // Record PC so we can determine if next instruction is sequential or not 1.802 - pc_c <= #1 pc_w; 1.803 + pc_c <= pc_w; 1.804 // Indicate if it was an eret/bret instruction 1.805 - trace_eret <= #1 eret_w; 1.806 + trace_eret <= eret_w; 1.807 `ifdef CFG_DEBUG_ENABLED 1.808 - trace_bret <= #1 bret_w; 1.809 + trace_bret <= bret_w; 1.810 `endif 1.811 end 1.812 else 1.813 begin 1.814 - trace_eret <= #1 `FALSE; 1.815 + trace_eret <= `FALSE; 1.816 `ifdef CFG_DEBUG_ENABLED 1.817 - trace_bret <= #1 `FALSE; 1.818 + trace_bret <= `FALSE; 1.819 `endif 1.820 end 1.821 end
2.1 --- a/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 2.2 +++ b/lm32_dcache.v Sat Aug 06 01:26:56 2011 +0100 2.3 @@ -441,11 +441,11 @@ 2.4 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.5 begin 2.6 if (rst_i == `TRUE) 2.7 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 2.8 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 2.9 else 2.10 begin 2.11 if (refill_request == `TRUE) 2.12 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 2.13 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 2.14 end 2.15 end 2.16 end 2.17 @@ -455,9 +455,9 @@ 2.18 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.19 begin 2.20 if (rst_i == `TRUE) 2.21 - refilling <= #1 `FALSE; 2.22 + refilling <= `FALSE; 2.23 else 2.24 - refilling <= #1 refill; 2.25 + refilling <= refill; 2.26 end 2.27 2.28 // Instruction cache control FSM 2.29 @@ -465,11 +465,11 @@ 2.30 begin 2.31 if (rst_i == `TRUE) 2.32 begin 2.33 - state <= #1 `LM32_DC_STATE_FLUSH; 2.34 - flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 2.35 - refill_request <= #1 `FALSE; 2.36 - refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 2.37 - restart_request <= #1 `FALSE; 2.38 + state <= `LM32_DC_STATE_FLUSH; 2.39 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 2.40 + refill_request <= `FALSE; 2.41 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 2.42 + restart_request <= `FALSE; 2.43 end 2.44 else 2.45 begin 2.46 @@ -479,35 +479,35 @@ 2.47 `LM32_DC_STATE_FLUSH: 2.48 begin 2.49 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 2.50 - state <= #1 `LM32_DC_STATE_CHECK; 2.51 - flush_set <= #1 flush_set - 1'b1; 2.52 + state <= `LM32_DC_STATE_CHECK; 2.53 + flush_set <= flush_set - 1'b1; 2.54 end 2.55 2.56 // Check for cache misses 2.57 `LM32_DC_STATE_CHECK: 2.58 begin 2.59 if (stall_a == `FALSE) 2.60 - restart_request <= #1 `FALSE; 2.61 + restart_request <= `FALSE; 2.62 if (miss == `TRUE) 2.63 begin 2.64 - refill_request <= #1 `TRUE; 2.65 - refill_address <= #1 address_m; 2.66 - state <= #1 `LM32_DC_STATE_REFILL; 2.67 + refill_request <= `TRUE; 2.68 + refill_address <= address_m; 2.69 + state <= `LM32_DC_STATE_REFILL; 2.70 end 2.71 else if (dflush == `TRUE) 2.72 - state <= #1 `LM32_DC_STATE_FLUSH; 2.73 + state <= `LM32_DC_STATE_FLUSH; 2.74 end 2.75 2.76 // Refill a cache line 2.77 `LM32_DC_STATE_REFILL: 2.78 begin 2.79 - refill_request <= #1 `FALSE; 2.80 + refill_request <= `FALSE; 2.81 if (refill_ready == `TRUE) 2.82 begin 2.83 if (last_refill == `TRUE) 2.84 begin 2.85 - restart_request <= #1 `TRUE; 2.86 - state <= #1 `LM32_DC_STATE_CHECK; 2.87 + restart_request <= `TRUE; 2.88 + state <= `LM32_DC_STATE_CHECK; 2.89 end 2.90 end 2.91 end 2.92 @@ -523,7 +523,7 @@ 2.93 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.94 begin 2.95 if (rst_i == `TRUE) 2.96 - refill_offset <= #1 {addr_offset_width{1'b0}}; 2.97 + refill_offset <= {addr_offset_width{1'b0}}; 2.98 else 2.99 begin 2.100 case (state) 2.101 @@ -532,14 +532,14 @@ 2.102 `LM32_DC_STATE_CHECK: 2.103 begin 2.104 if (miss == `TRUE) 2.105 - refill_offset <= #1 {addr_offset_width{1'b0}}; 2.106 + refill_offset <= {addr_offset_width{1'b0}}; 2.107 end 2.108 2.109 // Refill a cache line 2.110 `LM32_DC_STATE_REFILL: 2.111 begin 2.112 if (refill_ready == `TRUE) 2.113 - refill_offset <= #1 refill_offset + 1'b1; 2.114 + refill_offset <= refill_offset + 1'b1; 2.115 end 2.116 2.117 endcase
3.1 --- a/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 3.2 +++ b/lm32_debug.v Sat Aug 06 01:26:56 2011 +0100 3.3 @@ -247,15 +247,15 @@ 3.4 begin 3.5 if (rst_i == `TRUE) 3.6 begin 3.7 - bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 3.8 - bp_e[i] <= #1 `FALSE; 3.9 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 3.10 + bp_e[i] <= `FALSE; 3.11 end 3.12 else 3.13 begin 3.14 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 3.15 begin 3.16 - bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 3.17 - bp_e[i] <= #1 debug_csr_write_data[0]; 3.18 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 3.19 + bp_e[i] <= debug_csr_write_data[0]; 3.20 end 3.21 end 3.22 end 3.23 @@ -270,17 +270,17 @@ 3.24 begin 3.25 if (rst_i == `TRUE) 3.26 begin 3.27 - wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 3.28 - wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 3.29 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 3.30 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 3.31 end 3.32 else 3.33 begin 3.34 if (debug_csr_write_enable == `TRUE) 3.35 begin 3.36 if (debug_csr == `LM32_CSR_DC) 3.37 - wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 3.38 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 3.39 if (debug_csr == `LM32_CSR_WP0 + i) 3.40 - wp[i] <= #1 debug_csr_write_data; 3.41 + wp[i] <= debug_csr_write_data; 3.42 end 3.43 end 3.44 end 3.45 @@ -291,11 +291,11 @@ 3.46 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 3.47 begin 3.48 if (rst_i == `TRUE) 3.49 - dc_re <= #1 `FALSE; 3.50 + dc_re <= `FALSE; 3.51 else 3.52 begin 3.53 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 3.54 - dc_re <= #1 debug_csr_write_data[1]; 3.55 + dc_re <= debug_csr_write_data[1]; 3.56 end 3.57 end 3.58 3.59 @@ -305,18 +305,18 @@ 3.60 begin 3.61 if (rst_i == `TRUE) 3.62 begin 3.63 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.64 - dc_ss <= #1 `FALSE; 3.65 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.66 + dc_ss <= `FALSE; 3.67 end 3.68 else 3.69 begin 3.70 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 3.71 begin 3.72 - dc_ss <= #1 debug_csr_write_data[0]; 3.73 + dc_ss <= debug_csr_write_data[0]; 3.74 if (debug_csr_write_data[0] == `FALSE) 3.75 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.76 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.77 else 3.78 - state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 3.79 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 3.80 end 3.81 case (state) 3.82 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 3.83 @@ -327,26 +327,26 @@ 3.84 ) 3.85 && (stall_x == `FALSE) 3.86 ) 3.87 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.88 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.89 end 3.90 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 3.91 begin 3.92 // Wait for an instruction to be executed 3.93 if ((q_x == `TRUE) && (stall_x == `FALSE)) 3.94 - state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 3.95 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 3.96 end 3.97 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 3.98 begin 3.99 // Wait for exception to be raised 3.100 `ifdef CFG_DCACHE_ENABLED 3.101 if (dcache_refill_request == `TRUE) 3.102 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.103 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.104 else 3.105 `endif 3.106 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 3.107 begin 3.108 - dc_ss <= #1 `FALSE; 3.109 - state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 3.110 + dc_ss <= `FALSE; 3.111 + state <= `LM32_DEBUG_SS_STATE_RESTART; 3.112 end 3.113 end 3.114 `LM32_DEBUG_SS_STATE_RESTART: 3.115 @@ -354,10 +354,10 @@ 3.116 // Watch to see if stepped instruction is restarted due to a cache miss 3.117 `ifdef CFG_DCACHE_ENABLED 3.118 if (dcache_refill_request == `TRUE) 3.119 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.120 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.121 else 3.122 `endif 3.123 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.124 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.125 end 3.126 endcase 3.127 end
4.1 --- a/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 4.2 +++ b/lm32_icache.v Sat Aug 06 01:26:56 2011 +0100 4.3 @@ -380,11 +380,11 @@ 4.4 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.5 begin 4.6 if (rst_i == `TRUE) 4.7 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 4.8 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 4.9 else 4.10 begin 4.11 if (miss == `TRUE) 4.12 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 4.13 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 4.14 end 4.15 end 4.16 end 4.17 @@ -394,9 +394,9 @@ 4.18 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.19 begin 4.20 if (rst_i == `TRUE) 4.21 - refilling <= #1 `FALSE; 4.22 + refilling <= `FALSE; 4.23 else 4.24 - refilling <= #1 refill; 4.25 + refilling <= refill; 4.26 end 4.27 4.28 // Instruction cache control FSM 4.29 @@ -404,10 +404,10 @@ 4.30 begin 4.31 if (rst_i == `TRUE) 4.32 begin 4.33 - state <= #1 `LM32_IC_STATE_FLUSH_INIT; 4.34 - flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 4.35 - refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 4.36 - restart_request <= #1 `FALSE; 4.37 + state <= `LM32_IC_STATE_FLUSH_INIT; 4.38 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 4.39 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 4.40 + restart_request <= `FALSE; 4.41 end 4.42 else 4.43 begin 4.44 @@ -417,8 +417,8 @@ 4.45 `LM32_IC_STATE_FLUSH_INIT: 4.46 begin 4.47 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 4.48 - state <= #1 `LM32_IC_STATE_CHECK; 4.49 - flush_set <= #1 flush_set - 1'b1; 4.50 + state <= `LM32_IC_STATE_CHECK; 4.51 + flush_set <= flush_set - 1'b1; 4.52 end 4.53 4.54 // Flush the cache in response to an write to the ICC CSR 4.55 @@ -427,28 +427,28 @@ 4.56 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 4.57 `ifdef CFG_IROM_ENABLED 4.58 if (select_f) 4.59 - state <= #1 `LM32_IC_STATE_REFILL; 4.60 + state <= `LM32_IC_STATE_REFILL; 4.61 else 4.62 `endif 4.63 - state <= #1 `LM32_IC_STATE_CHECK; 4.64 + state <= `LM32_IC_STATE_CHECK; 4.65 4.66 - flush_set <= #1 flush_set - 1'b1; 4.67 + flush_set <= flush_set - 1'b1; 4.68 end 4.69 4.70 // Check for cache misses 4.71 `LM32_IC_STATE_CHECK: 4.72 begin 4.73 if (stall_a == `FALSE) 4.74 - restart_request <= #1 `FALSE; 4.75 + restart_request <= `FALSE; 4.76 if (iflush == `TRUE) 4.77 begin 4.78 - refill_address <= #1 address_f; 4.79 - state <= #1 `LM32_IC_STATE_FLUSH; 4.80 + refill_address <= address_f; 4.81 + state <= `LM32_IC_STATE_FLUSH; 4.82 end 4.83 else if (miss == `TRUE) 4.84 begin 4.85 - refill_address <= #1 address_f; 4.86 - state <= #1 `LM32_IC_STATE_REFILL; 4.87 + refill_address <= address_f; 4.88 + state <= `LM32_IC_STATE_REFILL; 4.89 end 4.90 end 4.91 4.92 @@ -459,8 +459,8 @@ 4.93 begin 4.94 if (last_refill == `TRUE) 4.95 begin 4.96 - restart_request <= #1 `TRUE; 4.97 - state <= #1 `LM32_IC_STATE_CHECK; 4.98 + restart_request <= `TRUE; 4.99 + state <= `LM32_IC_STATE_CHECK; 4.100 end 4.101 end 4.102 end 4.103 @@ -476,7 +476,7 @@ 4.104 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.105 begin 4.106 if (rst_i == `TRUE) 4.107 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.108 + refill_offset <= {addr_offset_width{1'b0}}; 4.109 else 4.110 begin 4.111 case (state) 4.112 @@ -485,16 +485,16 @@ 4.113 `LM32_IC_STATE_CHECK: 4.114 begin 4.115 if (iflush == `TRUE) 4.116 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.117 + refill_offset <= {addr_offset_width{1'b0}}; 4.118 else if (miss == `TRUE) 4.119 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.120 + refill_offset <= {addr_offset_width{1'b0}}; 4.121 end 4.122 4.123 // Refill a cache line 4.124 `LM32_IC_STATE_REFILL: 4.125 begin 4.126 if (refill_ready == `TRUE) 4.127 - refill_offset <= #1 refill_offset + 1'b1; 4.128 + refill_offset <= refill_offset + 1'b1; 4.129 end 4.130 4.131 endcase
5.1 --- a/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 5.2 +++ b/lm32_instruction_unit.v Sat Aug 06 01:26:56 2011 +0100 5.3 @@ -587,31 +587,31 @@ 5.4 `ifdef CFG_DEBUG_ENABLED 5.5 `ifdef CFG_ALTERNATE_EBA 5.6 if (at_debug == `TRUE) 5.7 - pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 5.8 + pc_f <= (`CFG_DEBA_RESET-4)/4; 5.9 else 5.10 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.11 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.12 `else 5.13 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.14 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.15 `endif 5.16 `else 5.17 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.18 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.19 `endif 5.20 - pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.21 - pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.22 - pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.23 - pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.24 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 5.25 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 5.26 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 5.27 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 5.28 end 5.29 else 5.30 begin 5.31 if (stall_f == `FALSE) 5.32 - pc_f <= #1 pc_a; 5.33 + pc_f <= pc_a; 5.34 if (stall_d == `FALSE) 5.35 - pc_d <= #1 pc_f; 5.36 + pc_d <= pc_f; 5.37 if (stall_x == `FALSE) 5.38 - pc_x <= #1 pc_d; 5.39 + pc_x <= pc_d; 5.40 if (stall_m == `FALSE) 5.41 - pc_m <= #1 pc_x; 5.42 - pc_w <= #1 pc_m; 5.43 + pc_m <= pc_x; 5.44 + pc_w <= pc_m; 5.45 end 5.46 end 5.47 5.48 @@ -620,24 +620,24 @@ 5.49 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 5.50 begin 5.51 if (rst_i == `TRUE) 5.52 - restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.53 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 5.54 else 5.55 begin 5.56 `ifdef CFG_DCACHE_ENABLED 5.57 `ifdef CFG_ICACHE_ENABLED 5.58 // D-cache restart address must take priority, otherwise instructions will be lost 5.59 if (dcache_refill_request == `TRUE) 5.60 - restart_address <= #1 pc_w; 5.61 + restart_address <= pc_w; 5.62 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 5.63 - restart_address <= #1 icache_refill_address; 5.64 + restart_address <= icache_refill_address; 5.65 `else 5.66 if (dcache_refill_request == `TRUE) 5.67 - restart_address <= #1 pc_w; 5.68 + restart_address <= pc_w; 5.69 `endif 5.70 `else 5.71 `ifdef CFG_ICACHE_ENABLED 5.72 if (icache_refill_request == `TRUE) 5.73 - restart_address <= #1 icache_refill_address; 5.74 + restart_address <= icache_refill_address; 5.75 `endif 5.76 `endif 5.77 end 5.78 @@ -649,11 +649,11 @@ 5.79 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 5.80 begin 5.81 if (rst_i == `TRUE) 5.82 - irom_select_f <= #1 `FALSE; 5.83 + irom_select_f <= `FALSE; 5.84 else 5.85 begin 5.86 if (stall_f == `FALSE) 5.87 - irom_select_f <= #1 irom_select_a; 5.88 + irom_select_f <= irom_select_a; 5.89 end 5.90 end 5.91 `endif 5.92 @@ -678,25 +678,25 @@ 5.93 begin 5.94 if (rst_i == `TRUE) 5.95 begin 5.96 - i_cyc_o <= #1 `FALSE; 5.97 - i_stb_o <= #1 `FALSE; 5.98 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 5.99 - i_cti_o <= #1 `LM32_CTYPE_END; 5.100 - i_lock_o <= #1 `FALSE; 5.101 - icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.102 - icache_refill_ready <= #1 `FALSE; 5.103 + i_cyc_o <= `FALSE; 5.104 + i_stb_o <= `FALSE; 5.105 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 5.106 + i_cti_o <= `LM32_CTYPE_END; 5.107 + i_lock_o <= `FALSE; 5.108 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.109 + icache_refill_ready <= `FALSE; 5.110 `ifdef CFG_BUS_ERRORS_ENABLED 5.111 - bus_error_f <= #1 `FALSE; 5.112 + bus_error_f <= `FALSE; 5.113 `endif 5.114 `ifdef CFG_HW_DEBUG_ENABLED 5.115 - i_we_o <= #1 `FALSE; 5.116 - i_sel_o <= #1 4'b1111; 5.117 - jtag_access <= #1 `FALSE; 5.118 + i_we_o <= `FALSE; 5.119 + i_sel_o <= 4'b1111; 5.120 + jtag_access <= `FALSE; 5.121 `endif 5.122 end 5.123 else 5.124 begin 5.125 - icache_refill_ready <= #1 `FALSE; 5.126 + icache_refill_ready <= `FALSE; 5.127 // Is a cycle in progress? 5.128 if (i_cyc_o == `TRUE) 5.129 begin 5.130 @@ -706,10 +706,10 @@ 5.131 `ifdef CFG_HW_DEBUG_ENABLED 5.132 if (jtag_access == `TRUE) 5.133 begin 5.134 - i_cyc_o <= #1 `FALSE; 5.135 - i_stb_o <= #1 `FALSE; 5.136 - i_we_o <= #1 `FALSE; 5.137 - jtag_access <= #1 `FALSE; 5.138 + i_cyc_o <= `FALSE; 5.139 + i_stb_o <= `FALSE; 5.140 + i_we_o <= `FALSE; 5.141 + jtag_access <= `FALSE; 5.142 end 5.143 else 5.144 `endif 5.145 @@ -717,22 +717,22 @@ 5.146 if (last_word == `TRUE) 5.147 begin 5.148 // Cache line fill complete 5.149 - i_cyc_o <= #1 `FALSE; 5.150 - i_stb_o <= #1 `FALSE; 5.151 - i_lock_o <= #1 `FALSE; 5.152 + i_cyc_o <= `FALSE; 5.153 + i_stb_o <= `FALSE; 5.154 + i_lock_o <= `FALSE; 5.155 end 5.156 // Fetch next word in cache line 5.157 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 5.158 - i_cti_o <= #1 next_cycle_type; 5.159 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 5.160 + i_cti_o <= next_cycle_type; 5.161 // Write fetched data into instruction cache 5.162 - icache_refill_ready <= #1 `TRUE; 5.163 - icache_refill_data <= #1 i_dat_i; 5.164 + icache_refill_ready <= `TRUE; 5.165 + icache_refill_data <= i_dat_i; 5.166 end 5.167 end 5.168 `ifdef CFG_BUS_ERRORS_ENABLED 5.169 if (i_err_i == `TRUE) 5.170 begin 5.171 - bus_error_f <= #1 `TRUE; 5.172 + bus_error_f <= `TRUE; 5.173 $display ("Instruction bus error. Address: %x", i_adr_o); 5.174 end 5.175 `endif 5.176 @@ -743,15 +743,15 @@ 5.177 begin 5.178 // Read first word of cache line 5.179 `ifdef CFG_HW_DEBUG_ENABLED 5.180 - i_sel_o <= #1 4'b1111; 5.181 + i_sel_o <= 4'b1111; 5.182 `endif 5.183 - i_adr_o <= #1 {first_address, 2'b00}; 5.184 - i_cyc_o <= #1 `TRUE; 5.185 - i_stb_o <= #1 `TRUE; 5.186 - i_cti_o <= #1 first_cycle_type; 5.187 - //i_lock_o <= #1 `TRUE; 5.188 + i_adr_o <= {first_address, 2'b00}; 5.189 + i_cyc_o <= `TRUE; 5.190 + i_stb_o <= `TRUE; 5.191 + i_cti_o <= first_cycle_type; 5.192 + //i_lock_o <= `TRUE; 5.193 `ifdef CFG_BUS_ERRORS_ENABLED 5.194 - bus_error_f <= #1 `FALSE; 5.195 + bus_error_f <= `FALSE; 5.196 `endif 5.197 end 5.198 `ifdef CFG_HW_DEBUG_ENABLED 5.199 @@ -760,18 +760,18 @@ 5.200 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 5.201 begin 5.202 case (jtag_address[1:0]) 5.203 - 2'b00: i_sel_o <= #1 4'b1000; 5.204 - 2'b01: i_sel_o <= #1 4'b0100; 5.205 - 2'b10: i_sel_o <= #1 4'b0010; 5.206 - 2'b11: i_sel_o <= #1 4'b0001; 5.207 + 2'b00: i_sel_o <= 4'b1000; 5.208 + 2'b01: i_sel_o <= 4'b0100; 5.209 + 2'b10: i_sel_o <= 4'b0010; 5.210 + 2'b11: i_sel_o <= 4'b0001; 5.211 endcase 5.212 - i_adr_o <= #1 jtag_address; 5.213 - i_dat_o <= #1 {4{jtag_write_data}}; 5.214 - i_cyc_o <= #1 `TRUE; 5.215 - i_stb_o <= #1 `TRUE; 5.216 - i_we_o <= #1 jtag_write_enable; 5.217 - i_cti_o <= #1 `LM32_CTYPE_END; 5.218 - jtag_access <= #1 `TRUE; 5.219 + i_adr_o <= jtag_address; 5.220 + i_dat_o <= {4{jtag_write_data}}; 5.221 + i_cyc_o <= `TRUE; 5.222 + i_stb_o <= `TRUE; 5.223 + i_we_o <= jtag_write_enable; 5.224 + i_cti_o <= `LM32_CTYPE_END; 5.225 + jtag_access <= `TRUE; 5.226 end 5.227 end 5.228 `endif 5.229 @@ -780,10 +780,10 @@ 5.230 // continually generated if exception handler is cached 5.231 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 5.232 if (branch_taken_x == `TRUE) 5.233 - bus_error_f <= #1 `FALSE; 5.234 + bus_error_f <= `FALSE; 5.235 `endif 5.236 if (branch_taken_m == `TRUE) 5.237 - bus_error_f <= #1 `FALSE; 5.238 + bus_error_f <= `FALSE; 5.239 `endif 5.240 end 5.241 end 5.242 @@ -793,14 +793,14 @@ 5.243 begin 5.244 if (rst_i == `TRUE) 5.245 begin 5.246 - i_cyc_o <= #1 `FALSE; 5.247 - i_stb_o <= #1 `FALSE; 5.248 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 5.249 - i_cti_o <= #1 `LM32_CTYPE_END; 5.250 - i_lock_o <= #1 `FALSE; 5.251 - wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.252 + i_cyc_o <= `FALSE; 5.253 + i_stb_o <= `FALSE; 5.254 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 5.255 + i_cti_o <= `LM32_CTYPE_END; 5.256 + i_lock_o <= `FALSE; 5.257 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.258 `ifdef CFG_BUS_ERRORS_ENABLED 5.259 - bus_error_f <= #1 `FALSE; 5.260 + bus_error_f <= `FALSE; 5.261 `endif 5.262 end 5.263 else 5.264 @@ -812,15 +812,15 @@ 5.265 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 5.266 begin 5.267 // Cycle complete 5.268 - i_cyc_o <= #1 `FALSE; 5.269 - i_stb_o <= #1 `FALSE; 5.270 + i_cyc_o <= `FALSE; 5.271 + i_stb_o <= `FALSE; 5.272 // Register fetched instruction 5.273 - wb_data_f <= #1 i_dat_i; 5.274 + wb_data_f <= i_dat_i; 5.275 end 5.276 `ifdef CFG_BUS_ERRORS_ENABLED 5.277 if (i_err_i == `TRUE) 5.278 begin 5.279 - bus_error_f <= #1 `TRUE; 5.280 + bus_error_f <= `TRUE; 5.281 $display ("Instruction bus error. Address: %x", i_adr_o); 5.282 end 5.283 `endif 5.284 @@ -836,13 +836,13 @@ 5.285 begin 5.286 // Fetch instruction 5.287 `ifdef CFG_HW_DEBUG_ENABLED 5.288 - i_sel_o <= #1 4'b1111; 5.289 + i_sel_o <= 4'b1111; 5.290 `endif 5.291 - i_adr_o <= #1 {pc_a, 2'b00}; 5.292 - i_cyc_o <= #1 `TRUE; 5.293 - i_stb_o <= #1 `TRUE; 5.294 + i_adr_o <= {pc_a, 2'b00}; 5.295 + i_cyc_o <= `TRUE; 5.296 + i_stb_o <= `TRUE; 5.297 `ifdef CFG_BUS_ERRORS_ENABLED 5.298 - bus_error_f <= #1 `FALSE; 5.299 + bus_error_f <= `FALSE; 5.300 `endif 5.301 end 5.302 else 5.303 @@ -854,7 +854,7 @@ 5.304 ) 5.305 begin 5.306 `ifdef CFG_BUS_ERRORS_ENABLED 5.307 - bus_error_f <= #1 `FALSE; 5.308 + bus_error_f <= `FALSE; 5.309 `endif 5.310 end 5.311 end 5.312 @@ -869,18 +869,18 @@ 5.313 begin 5.314 if (rst_i == `TRUE) 5.315 begin 5.316 - instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.317 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.318 `ifdef CFG_BUS_ERRORS_ENABLED 5.319 - bus_error_d <= #1 `FALSE; 5.320 + bus_error_d <= `FALSE; 5.321 `endif 5.322 end 5.323 else 5.324 begin 5.325 if (stall_d == `FALSE) 5.326 begin 5.327 - instruction_d <= #1 instruction_f; 5.328 + instruction_d <= instruction_f; 5.329 `ifdef CFG_BUS_ERRORS_ENABLED 5.330 - bus_error_d <= #1 bus_error_f; 5.331 + bus_error_d <= bus_error_f; 5.332 `endif 5.333 end 5.334 end
6.1 --- a/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 6.2 +++ b/lm32_interrupt.v Sat Aug 06 01:26:56 2011 +0100 6.3 @@ -220,64 +220,64 @@ 6.4 begin 6.5 if (rst_i == `TRUE) 6.6 begin 6.7 - ie <= #1 `FALSE; 6.8 - eie <= #1 `FALSE; 6.9 + ie <= `FALSE; 6.10 + eie <= `FALSE; 6.11 `ifdef CFG_DEBUG_ENABLED 6.12 - bie <= #1 `FALSE; 6.13 + bie <= `FALSE; 6.14 `endif 6.15 - im <= #1 {interrupts{1'b0}}; 6.16 - ip <= #1 {interrupts{1'b0}}; 6.17 + im <= {interrupts{1'b0}}; 6.18 + ip <= {interrupts{1'b0}}; 6.19 end 6.20 else 6.21 begin 6.22 // Set IP bit when interrupt line is asserted 6.23 - ip <= #1 asserted; 6.24 + ip <= asserted; 6.25 `ifdef CFG_DEBUG_ENABLED 6.26 if (non_debug_exception == `TRUE) 6.27 begin 6.28 // Save and then clear interrupt enable 6.29 - eie <= #1 ie; 6.30 - ie <= #1 `FALSE; 6.31 + eie <= ie; 6.32 + ie <= `FALSE; 6.33 end 6.34 else if (debug_exception == `TRUE) 6.35 begin 6.36 // Save and then clear interrupt enable 6.37 - bie <= #1 ie; 6.38 - ie <= #1 `FALSE; 6.39 + bie <= ie; 6.40 + ie <= `FALSE; 6.41 end 6.42 `else 6.43 if (exception == `TRUE) 6.44 begin 6.45 // Save and then clear interrupt enable 6.46 - eie <= #1 ie; 6.47 - ie <= #1 `FALSE; 6.48 + eie <= ie; 6.49 + ie <= `FALSE; 6.50 end 6.51 `endif 6.52 else if (stall_x == `FALSE) 6.53 begin 6.54 if (eret_q_x == `TRUE) 6.55 // Restore interrupt enable 6.56 - ie <= #1 eie; 6.57 + ie <= eie; 6.58 `ifdef CFG_DEBUG_ENABLED 6.59 else if (bret_q_x == `TRUE) 6.60 // Restore interrupt enable 6.61 - ie <= #1 bie; 6.62 + ie <= bie; 6.63 `endif 6.64 else if (csr_write_enable == `TRUE) 6.65 begin 6.66 // Handle wcsr write 6.67 if (csr == `LM32_CSR_IE) 6.68 begin 6.69 - ie <= #1 csr_write_data[0]; 6.70 - eie <= #1 csr_write_data[1]; 6.71 + ie <= csr_write_data[0]; 6.72 + eie <= csr_write_data[1]; 6.73 `ifdef CFG_DEBUG_ENABLED 6.74 - bie <= #1 csr_write_data[2]; 6.75 + bie <= csr_write_data[2]; 6.76 `endif 6.77 end 6.78 if (csr == `LM32_CSR_IM) 6.79 - im <= #1 csr_write_data[interrupts-1:0]; 6.80 + im <= csr_write_data[interrupts-1:0]; 6.81 if (csr == `LM32_CSR_IP) 6.82 - ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 6.83 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 6.84 end 6.85 end 6.86 end 6.87 @@ -290,61 +290,61 @@ 6.88 begin 6.89 if (rst_i == `TRUE) 6.90 begin 6.91 - ie <= #1 `FALSE; 6.92 - eie <= #1 `FALSE; 6.93 + ie <= `FALSE; 6.94 + eie <= `FALSE; 6.95 `ifdef CFG_DEBUG_ENABLED 6.96 - bie <= #1 `FALSE; 6.97 + bie <= `FALSE; 6.98 `endif 6.99 - ip <= #1 {interrupts{1'b0}}; 6.100 + ip <= {interrupts{1'b0}}; 6.101 end 6.102 else 6.103 begin 6.104 // Set IP bit when interrupt line is asserted 6.105 - ip <= #1 asserted; 6.106 + ip <= asserted; 6.107 `ifdef CFG_DEBUG_ENABLED 6.108 if (non_debug_exception == `TRUE) 6.109 begin 6.110 // Save and then clear interrupt enable 6.111 - eie <= #1 ie; 6.112 - ie <= #1 `FALSE; 6.113 + eie <= ie; 6.114 + ie <= `FALSE; 6.115 end 6.116 else if (debug_exception == `TRUE) 6.117 begin 6.118 // Save and then clear interrupt enable 6.119 - bie <= #1 ie; 6.120 - ie <= #1 `FALSE; 6.121 + bie <= ie; 6.122 + ie <= `FALSE; 6.123 end 6.124 `else 6.125 if (exception == `TRUE) 6.126 begin 6.127 // Save and then clear interrupt enable 6.128 - eie <= #1 ie; 6.129 - ie <= #1 `FALSE; 6.130 + eie <= ie; 6.131 + ie <= `FALSE; 6.132 end 6.133 `endif 6.134 else if (stall_x == `FALSE) 6.135 begin 6.136 if (eret_q_x == `TRUE) 6.137 // Restore interrupt enable 6.138 - ie <= #1 eie; 6.139 + ie <= eie; 6.140 `ifdef CFG_DEBUG_ENABLED 6.141 else if (bret_q_x == `TRUE) 6.142 // Restore interrupt enable 6.143 - ie <= #1 bie; 6.144 + ie <= bie; 6.145 `endif 6.146 else if (csr_write_enable == `TRUE) 6.147 begin 6.148 // Handle wcsr write 6.149 if (csr == `LM32_CSR_IE) 6.150 begin 6.151 - ie <= #1 csr_write_data[0]; 6.152 - eie <= #1 csr_write_data[1]; 6.153 + ie <= csr_write_data[0]; 6.154 + eie <= csr_write_data[1]; 6.155 `ifdef CFG_DEBUG_ENABLED 6.156 - bie <= #1 csr_write_data[2]; 6.157 + bie <= csr_write_data[2]; 6.158 `endif 6.159 end 6.160 if (csr == `LM32_CSR_IP) 6.161 - ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 6.162 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 6.163 end 6.164 end 6.165 end
7.1 --- a/lm32_jtag.v Sat Aug 06 00:02:46 2011 +0100 7.2 +++ b/lm32_jtag.v Sat Aug 06 01:26:56 2011 +0100 7.3 @@ -257,9 +257,9 @@ 7.4 always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 7.5 begin 7.6 if (rst_i == `TRUE) 7.7 - rx_toggle <= #1 1'b0; 7.8 + rx_toggle <= 1'b0; 7.9 else 7.10 - rx_toggle <= #1 ~rx_toggle; 7.11 + rx_toggle <= ~rx_toggle; 7.12 end 7.13 7.14 always @(*) 7.15 @@ -273,15 +273,15 @@ 7.16 begin 7.17 if (rst_i == `TRUE) 7.18 begin 7.19 - rx_toggle_r <= #1 1'b0; 7.20 - rx_toggle_r_r <= #1 1'b0; 7.21 - rx_toggle_r_r_r <= #1 1'b0; 7.22 + rx_toggle_r <= 1'b0; 7.23 + rx_toggle_r_r <= 1'b0; 7.24 + rx_toggle_r_r_r <= 1'b0; 7.25 end 7.26 else 7.27 begin 7.28 - rx_toggle_r <= #1 rx_toggle; 7.29 - rx_toggle_r_r <= #1 rx_toggle_r; 7.30 - rx_toggle_r_r_r <= #1 rx_toggle_r_r; 7.31 + rx_toggle_r <= rx_toggle; 7.32 + rx_toggle_r_r <= rx_toggle_r; 7.33 + rx_toggle_r_r_r <= rx_toggle_r_r; 7.34 end 7.35 end 7.36 7.37 @@ -290,24 +290,24 @@ 7.38 begin 7.39 if (rst_i == `TRUE) 7.40 begin 7.41 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.42 - command <= #1 4'b0000; 7.43 - jtag_reg_d <= #1 8'h00; 7.44 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.45 + command <= 4'b0000; 7.46 + jtag_reg_d <= 8'h00; 7.47 `ifdef CFG_HW_DEBUG_ENABLED 7.48 - processing <= #1 `FALSE; 7.49 - jtag_csr_write_enable <= #1 `FALSE; 7.50 - jtag_read_enable <= #1 `FALSE; 7.51 - jtag_write_enable <= #1 `FALSE; 7.52 + processing <= `FALSE; 7.53 + jtag_csr_write_enable <= `FALSE; 7.54 + jtag_read_enable <= `FALSE; 7.55 + jtag_write_enable <= `FALSE; 7.56 `endif 7.57 `ifdef CFG_DEBUG_ENABLED 7.58 - jtag_break <= #1 `FALSE; 7.59 - jtag_reset <= #1 `FALSE; 7.60 + jtag_break <= `FALSE; 7.61 + jtag_reset <= `FALSE; 7.62 `endif 7.63 `ifdef CFG_JTAG_UART_ENABLED 7.64 - uart_tx_byte <= #1 8'h00; 7.65 - uart_tx_valid <= #1 `FALSE; 7.66 - uart_rx_byte <= #1 8'h00; 7.67 - uart_rx_valid <= #1 `FALSE; 7.68 + uart_tx_byte <= 8'h00; 7.69 + uart_tx_valid <= `FALSE; 7.70 + uart_rx_byte <= 8'h00; 7.71 + uart_rx_valid <= `FALSE; 7.72 `endif 7.73 end 7.74 else 7.75 @@ -319,13 +319,13 @@ 7.76 `LM32_CSR_JTX: 7.77 begin 7.78 // Set flag indicating data is available 7.79 - uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG]; 7.80 - uart_tx_valid <= #1 `TRUE; 7.81 + uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 7.82 + uart_tx_valid <= `TRUE; 7.83 end 7.84 `LM32_CSR_JRX: 7.85 begin 7.86 // Clear flag indidicating data has been received 7.87 - uart_rx_valid <= #1 `FALSE; 7.88 + uart_rx_valid <= `FALSE; 7.89 end 7.90 endcase 7.91 end 7.92 @@ -334,8 +334,8 @@ 7.93 // When an exception has occured, clear the requests 7.94 if (exception_q_w == `TRUE) 7.95 begin 7.96 - jtag_break <= #1 `FALSE; 7.97 - jtag_reset <= #1 `FALSE; 7.98 + jtag_break <= `FALSE; 7.99 + jtag_reset <= `FALSE; 7.100 end 7.101 `endif 7.102 case (state) 7.103 @@ -344,7 +344,7 @@ 7.104 // Wait for rx register to toggle which indicates new data is available 7.105 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.106 begin 7.107 - command <= #1 rx_byte[7:4]; 7.108 + command <= rx_byte[7:4]; 7.109 case (rx_addr) 7.110 `ifdef CFG_DEBUG_ENABLED 7.111 `LM32_DP: 7.112 @@ -352,37 +352,37 @@ 7.113 case (rx_byte[7:4]) 7.114 `ifdef CFG_HW_DEBUG_ENABLED 7.115 `LM32_DP_READ_MEMORY: 7.116 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.117 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.118 `LM32_DP_READ_SEQUENTIAL: 7.119 begin 7.120 - {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 7.121 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.122 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 7.123 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.124 end 7.125 `LM32_DP_WRITE_MEMORY: 7.126 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.127 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.128 `LM32_DP_WRITE_SEQUENTIAL: 7.129 begin 7.130 - {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 7.131 - state <= #1 5; 7.132 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 7.133 + state <= 5; 7.134 end 7.135 `LM32_DP_WRITE_CSR: 7.136 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.137 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.138 `endif 7.139 `LM32_DP_BREAK: 7.140 begin 7.141 `ifdef CFG_JTAG_UART_ENABLED 7.142 - uart_rx_valid <= #1 `FALSE; 7.143 - uart_tx_valid <= #1 `FALSE; 7.144 + uart_rx_valid <= `FALSE; 7.145 + uart_tx_valid <= `FALSE; 7.146 `endif 7.147 - jtag_break <= #1 `TRUE; 7.148 + jtag_break <= `TRUE; 7.149 end 7.150 `LM32_DP_RESET: 7.151 begin 7.152 `ifdef CFG_JTAG_UART_ENABLED 7.153 - uart_rx_valid <= #1 `FALSE; 7.154 - uart_tx_valid <= #1 `FALSE; 7.155 + uart_rx_valid <= `FALSE; 7.156 + uart_tx_valid <= `FALSE; 7.157 `endif 7.158 - jtag_reset <= #1 `TRUE; 7.159 + jtag_reset <= `TRUE; 7.160 end 7.161 endcase 7.162 end 7.163 @@ -390,13 +390,13 @@ 7.164 `ifdef CFG_JTAG_UART_ENABLED 7.165 `LM32_TX: 7.166 begin 7.167 - uart_rx_byte <= #1 rx_byte; 7.168 - uart_rx_valid <= #1 `TRUE; 7.169 + uart_rx_byte <= rx_byte; 7.170 + uart_rx_valid <= `TRUE; 7.171 end 7.172 `LM32_RX: 7.173 begin 7.174 - jtag_reg_d <= #1 uart_tx_byte; 7.175 - uart_tx_valid <= #1 `FALSE; 7.176 + jtag_reg_d <= uart_tx_byte; 7.177 + uart_tx_valid <= `FALSE; 7.178 end 7.179 `endif 7.180 default: 7.181 @@ -409,43 +409,43 @@ 7.182 begin 7.183 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.184 begin 7.185 - jtag_byte_0 <= #1 rx_byte; 7.186 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_1; 7.187 + jtag_byte_0 <= rx_byte; 7.188 + state <= `LM32_JTAG_STATE_READ_BYTE_1; 7.189 end 7.190 end 7.191 `LM32_JTAG_STATE_READ_BYTE_1: 7.192 begin 7.193 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.194 begin 7.195 - jtag_byte_1 <= #1 rx_byte; 7.196 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_2; 7.197 + jtag_byte_1 <= rx_byte; 7.198 + state <= `LM32_JTAG_STATE_READ_BYTE_2; 7.199 end 7.200 end 7.201 `LM32_JTAG_STATE_READ_BYTE_2: 7.202 begin 7.203 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.204 begin 7.205 - jtag_byte_2 <= #1 rx_byte; 7.206 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_3; 7.207 + jtag_byte_2 <= rx_byte; 7.208 + state <= `LM32_JTAG_STATE_READ_BYTE_3; 7.209 end 7.210 end 7.211 `LM32_JTAG_STATE_READ_BYTE_3: 7.212 begin 7.213 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.214 begin 7.215 - jtag_byte_3 <= #1 rx_byte; 7.216 + jtag_byte_3 <= rx_byte; 7.217 if (command == `LM32_DP_READ_MEMORY) 7.218 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.219 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.220 else 7.221 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_4; 7.222 + state <= `LM32_JTAG_STATE_READ_BYTE_4; 7.223 end 7.224 end 7.225 `LM32_JTAG_STATE_READ_BYTE_4: 7.226 begin 7.227 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.228 begin 7.229 - jtag_byte_4 <= #1 rx_byte; 7.230 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.231 + jtag_byte_4 <= rx_byte; 7.232 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.233 end 7.234 end 7.235 `LM32_JTAG_STATE_PROCESS_COMMAND: 7.236 @@ -454,22 +454,22 @@ 7.237 `LM32_DP_READ_MEMORY, 7.238 `LM32_DP_READ_SEQUENTIAL: 7.239 begin 7.240 - jtag_read_enable <= #1 `TRUE; 7.241 - processing <= #1 `TRUE; 7.242 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.243 + jtag_read_enable <= `TRUE; 7.244 + processing <= `TRUE; 7.245 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.246 end 7.247 `LM32_DP_WRITE_MEMORY, 7.248 `LM32_DP_WRITE_SEQUENTIAL: 7.249 begin 7.250 - jtag_write_enable <= #1 `TRUE; 7.251 - processing <= #1 `TRUE; 7.252 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.253 + jtag_write_enable <= `TRUE; 7.254 + processing <= `TRUE; 7.255 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.256 end 7.257 `LM32_DP_WRITE_CSR: 7.258 begin 7.259 - jtag_csr_write_enable <= #1 `TRUE; 7.260 - processing <= #1 `TRUE; 7.261 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR; 7.262 + jtag_csr_write_enable <= `TRUE; 7.263 + processing <= `TRUE; 7.264 + state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 7.265 end 7.266 endcase 7.267 end 7.268 @@ -477,18 +477,18 @@ 7.269 begin 7.270 if (jtag_access_complete == `TRUE) 7.271 begin 7.272 - jtag_read_enable <= #1 `FALSE; 7.273 - jtag_reg_d <= #1 jtag_read_data; 7.274 - jtag_write_enable <= #1 `FALSE; 7.275 - processing <= #1 `FALSE; 7.276 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.277 + jtag_read_enable <= `FALSE; 7.278 + jtag_reg_d <= jtag_read_data; 7.279 + jtag_write_enable <= `FALSE; 7.280 + processing <= `FALSE; 7.281 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.282 end 7.283 end 7.284 `LM32_JTAG_STATE_WAIT_FOR_CSR: 7.285 begin 7.286 - jtag_csr_write_enable <= #1 `FALSE; 7.287 - processing <= #1 `FALSE; 7.288 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.289 + jtag_csr_write_enable <= `FALSE; 7.290 + processing <= `FALSE; 7.291 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.292 end 7.293 `endif 7.294 endcase
8.1 --- a/lm32_load_store_unit.v Sat Aug 06 00:02:46 2011 +0100 8.2 +++ b/lm32_load_store_unit.v Sat Aug 06 01:26:56 2011 +0100 8.3 @@ -343,13 +343,13 @@ 8.4 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.5 if (rst_i == `TRUE) 8.6 begin 8.7 - dram_bypass_en <= #1 `FALSE; 8.8 - dram_bypass_data <= #1 0; 8.9 + dram_bypass_en <= `FALSE; 8.10 + dram_bypass_data <= 0; 8.11 end 8.12 else 8.13 begin 8.14 if (stall_x == `FALSE) 8.15 - dram_bypass_data <= #1 dram_store_data_m; 8.16 + dram_bypass_data <= dram_store_data_m; 8.17 8.18 if ( (stall_m == `FALSE) 8.19 && (stall_x == `FALSE) 8.20 @@ -359,12 +359,12 @@ 8.21 ) 8.22 && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 8.23 ) 8.24 - dram_bypass_en <= #1 `TRUE; 8.25 + dram_bypass_en <= `TRUE; 8.26 else 8.27 if ( (dram_bypass_en == `TRUE) 8.28 && (stall_x == `FALSE) 8.29 ) 8.30 - dram_bypass_en <= #1 `FALSE; 8.31 + dram_bypass_en <= `FALSE; 8.32 end 8.33 8.34 assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 8.35 @@ -624,26 +624,26 @@ 8.36 begin 8.37 if (rst_i == `TRUE) 8.38 begin 8.39 - d_cyc_o <= #1 `FALSE; 8.40 - d_stb_o <= #1 `FALSE; 8.41 - d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.42 - d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.43 - d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 8.44 - d_we_o <= #1 `FALSE; 8.45 - d_cti_o <= #1 `LM32_CTYPE_END; 8.46 - d_lock_o <= #1 `FALSE; 8.47 - wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.48 - wb_load_complete <= #1 `FALSE; 8.49 - stall_wb_load <= #1 `FALSE; 8.50 + d_cyc_o <= `FALSE; 8.51 + d_stb_o <= `FALSE; 8.52 + d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 8.53 + d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 8.54 + d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 8.55 + d_we_o <= `FALSE; 8.56 + d_cti_o <= `LM32_CTYPE_END; 8.57 + d_lock_o <= `FALSE; 8.58 + wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 8.59 + wb_load_complete <= `FALSE; 8.60 + stall_wb_load <= `FALSE; 8.61 `ifdef CFG_DCACHE_ENABLED 8.62 - dcache_refill_ready <= #1 `FALSE; 8.63 + dcache_refill_ready <= `FALSE; 8.64 `endif 8.65 end 8.66 else 8.67 begin 8.68 `ifdef CFG_DCACHE_ENABLED 8.69 // Refill ready should only be asserted for a single cycle 8.70 - dcache_refill_ready <= #1 `FALSE; 8.71 + dcache_refill_ready <= `FALSE; 8.72 `endif 8.73 // Is a Wishbone cycle already in progress? 8.74 if (d_cyc_o == `TRUE) 8.75 @@ -655,25 +655,25 @@ 8.76 if ((dcache_refilling == `TRUE) && (!last_word)) 8.77 begin 8.78 // Fetch next word of cache line 8.79 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 8.80 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 8.81 end 8.82 else 8.83 `endif 8.84 begin 8.85 // Refill/access complete 8.86 - d_cyc_o <= #1 `FALSE; 8.87 - d_stb_o <= #1 `FALSE; 8.88 - d_lock_o <= #1 `FALSE; 8.89 + d_cyc_o <= `FALSE; 8.90 + d_stb_o <= `FALSE; 8.91 + d_lock_o <= `FALSE; 8.92 end 8.93 `ifdef CFG_DCACHE_ENABLED 8.94 - d_cti_o <= #1 next_cycle_type; 8.95 + d_cti_o <= next_cycle_type; 8.96 // If we are performing a refill, indicate to cache next word of data is ready 8.97 - dcache_refill_ready <= #1 dcache_refilling; 8.98 + dcache_refill_ready <= dcache_refilling; 8.99 `endif 8.100 // Register data read from Wishbone interface 8.101 - wb_data_m <= #1 d_dat_i; 8.102 + wb_data_m <= d_dat_i; 8.103 // Don't set when stores complete - otherwise we'll deadlock if load in m stage 8.104 - wb_load_complete <= #1 !d_we_o; 8.105 + wb_load_complete <= !d_we_o; 8.106 end 8.107 // synthesis translate_off 8.108 if (d_err_i == `TRUE) 8.109 @@ -686,13 +686,13 @@ 8.110 if (dcache_refill_request == `TRUE) 8.111 begin 8.112 // Start cache refill 8.113 - d_adr_o <= #1 first_address; 8.114 - d_cyc_o <= #1 `TRUE; 8.115 - d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}}; 8.116 - d_stb_o <= #1 `TRUE; 8.117 - d_we_o <= #1 `FALSE; 8.118 - d_cti_o <= #1 first_cycle_type; 8.119 - //d_lock_o <= #1 `TRUE; 8.120 + d_adr_o <= first_address; 8.121 + d_cyc_o <= `TRUE; 8.122 + d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 8.123 + d_stb_o <= `TRUE; 8.124 + d_we_o <= `FALSE; 8.125 + d_cti_o <= first_cycle_type; 8.126 + //d_lock_o <= `TRUE; 8.127 end 8.128 else 8.129 `endif 8.130 @@ -707,13 +707,13 @@ 8.131 ) 8.132 begin 8.133 // Data cache is write through, so all stores go to memory 8.134 - d_dat_o <= #1 store_data_m; 8.135 - d_adr_o <= #1 load_store_address_m; 8.136 - d_cyc_o <= #1 `TRUE; 8.137 - d_sel_o <= #1 byte_enable_m; 8.138 - d_stb_o <= #1 `TRUE; 8.139 - d_we_o <= #1 `TRUE; 8.140 - d_cti_o <= #1 `LM32_CTYPE_END; 8.141 + d_dat_o <= store_data_m; 8.142 + d_adr_o <= load_store_address_m; 8.143 + d_cyc_o <= `TRUE; 8.144 + d_sel_o <= byte_enable_m; 8.145 + d_stb_o <= `TRUE; 8.146 + d_we_o <= `TRUE; 8.147 + d_cti_o <= `LM32_CTYPE_END; 8.148 end 8.149 else if ( (load_q_m == `TRUE) 8.150 && (wb_select_m == `TRUE) 8.151 @@ -722,24 +722,24 @@ 8.152 ) 8.153 begin 8.154 // Read requested address 8.155 - stall_wb_load <= #1 `FALSE; 8.156 - d_adr_o <= #1 load_store_address_m; 8.157 - d_cyc_o <= #1 `TRUE; 8.158 - d_sel_o <= #1 byte_enable_m; 8.159 - d_stb_o <= #1 `TRUE; 8.160 - d_we_o <= #1 `FALSE; 8.161 - d_cti_o <= #1 `LM32_CTYPE_END; 8.162 + stall_wb_load <= `FALSE; 8.163 + d_adr_o <= load_store_address_m; 8.164 + d_cyc_o <= `TRUE; 8.165 + d_sel_o <= byte_enable_m; 8.166 + d_stb_o <= `TRUE; 8.167 + d_we_o <= `FALSE; 8.168 + d_cti_o <= `LM32_CTYPE_END; 8.169 end 8.170 end 8.171 // Clear load/store complete flag when instruction leaves M stage 8.172 if (stall_m == `FALSE) 8.173 - wb_load_complete <= #1 `FALSE; 8.174 + wb_load_complete <= `FALSE; 8.175 // When a Wishbone load first enters the M stage, we need to stall it 8.176 if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 8.177 - stall_wb_load <= #1 `TRUE; 8.178 + stall_wb_load <= `TRUE; 8.179 // Clear stall request if load instruction is killed 8.180 if ((kill_m == `TRUE) || (exception_m == `TRUE)) 8.181 - stall_wb_load <= #1 `FALSE; 8.182 + stall_wb_load <= `FALSE; 8.183 end 8.184 end 8.185 8.186 @@ -750,39 +750,39 @@ 8.187 begin 8.188 if (rst_i == `TRUE) 8.189 begin 8.190 - sign_extend_m <= #1 `FALSE; 8.191 - size_m <= #1 2'b00; 8.192 - byte_enable_m <= #1 `FALSE; 8.193 - store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.194 + sign_extend_m <= `FALSE; 8.195 + size_m <= 2'b00; 8.196 + byte_enable_m <= `FALSE; 8.197 + store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 8.198 `ifdef CFG_DCACHE_ENABLED 8.199 - dcache_select_m <= #1 `FALSE; 8.200 + dcache_select_m <= `FALSE; 8.201 `endif 8.202 `ifdef CFG_DRAM_ENABLED 8.203 - dram_select_m <= #1 `FALSE; 8.204 + dram_select_m <= `FALSE; 8.205 `endif 8.206 `ifdef CFG_IROM_ENABLED 8.207 - irom_select_m <= #1 `FALSE; 8.208 + irom_select_m <= `FALSE; 8.209 `endif 8.210 - wb_select_m <= #1 `FALSE; 8.211 + wb_select_m <= `FALSE; 8.212 end 8.213 else 8.214 begin 8.215 if (stall_m == `FALSE) 8.216 begin 8.217 - sign_extend_m <= #1 sign_extend_x; 8.218 - size_m <= #1 size_x; 8.219 - byte_enable_m <= #1 byte_enable_x; 8.220 - store_data_m <= #1 store_data_x; 8.221 + sign_extend_m <= sign_extend_x; 8.222 + size_m <= size_x; 8.223 + byte_enable_m <= byte_enable_x; 8.224 + store_data_m <= store_data_x; 8.225 `ifdef CFG_DCACHE_ENABLED 8.226 - dcache_select_m <= #1 dcache_select_x; 8.227 + dcache_select_m <= dcache_select_x; 8.228 `endif 8.229 `ifdef CFG_DRAM_ENABLED 8.230 - dram_select_m <= #1 dram_select_x; 8.231 + dram_select_m <= dram_select_x; 8.232 `endif 8.233 `ifdef CFG_IROM_ENABLED 8.234 - irom_select_m <= #1 irom_select_x; 8.235 + irom_select_m <= irom_select_x; 8.236 `endif 8.237 - wb_select_m <= #1 wb_select_x; 8.238 + wb_select_m <= wb_select_x; 8.239 end 8.240 end 8.241 end 8.242 @@ -792,15 +792,15 @@ 8.243 begin 8.244 if (rst_i == `TRUE) 8.245 begin 8.246 - size_w <= #1 2'b00; 8.247 - data_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.248 - sign_extend_w <= #1 `FALSE; 8.249 + size_w <= 2'b00; 8.250 + data_w <= {`LM32_WORD_WIDTH{1'b0}}; 8.251 + sign_extend_w <= `FALSE; 8.252 end 8.253 else 8.254 begin 8.255 - size_w <= #1 size_m; 8.256 - data_w <= #1 data_m; 8.257 - sign_extend_w <= #1 sign_extend_m; 8.258 + size_w <= size_m; 8.259 + data_w <= data_m; 8.260 + sign_extend_w <= sign_extend_m; 8.261 end 8.262 end 8.263
9.1 --- a/lm32_mc_arithmetic.v Sat Aug 06 00:02:46 2011 +0100 9.2 +++ b/lm32_mc_arithmetic.v Sat Aug 06 01:26:56 2011 +0100 9.3 @@ -170,59 +170,59 @@ 9.4 begin 9.5 if (rst_i == `TRUE) 9.6 begin 9.7 - cycles <= #1 {6{1'b0}}; 9.8 - p <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.9 - a <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.10 - b <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.11 + cycles <= {6{1'b0}}; 9.12 + p <= {`LM32_WORD_WIDTH{1'b0}}; 9.13 + a <= {`LM32_WORD_WIDTH{1'b0}}; 9.14 + b <= {`LM32_WORD_WIDTH{1'b0}}; 9.15 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.16 - sign_extend_x <= #1 1'b0; 9.17 + sign_extend_x <= 1'b0; 9.18 `endif 9.19 `ifdef CFG_MC_DIVIDE_ENABLED 9.20 - divide_by_zero_x <= #1 `FALSE; 9.21 + divide_by_zero_x <= `FALSE; 9.22 `endif 9.23 - result_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.24 - state <= #1 `LM32_MC_STATE_IDLE; 9.25 + result_x <= {`LM32_WORD_WIDTH{1'b0}}; 9.26 + state <= `LM32_MC_STATE_IDLE; 9.27 end 9.28 else 9.29 begin 9.30 `ifdef CFG_MC_DIVIDE_ENABLED 9.31 - divide_by_zero_x <= #1 `FALSE; 9.32 + divide_by_zero_x <= `FALSE; 9.33 `endif 9.34 case (state) 9.35 `LM32_MC_STATE_IDLE: 9.36 begin 9.37 if (stall_d == `FALSE) 9.38 begin 9.39 - cycles <= #1 `LM32_WORD_WIDTH; 9.40 - p <= #1 32'b0; 9.41 - a <= #1 operand_0_d; 9.42 - b <= #1 operand_1_d; 9.43 + cycles <= `LM32_WORD_WIDTH; 9.44 + p <= 32'b0; 9.45 + a <= operand_0_d; 9.46 + b <= operand_1_d; 9.47 `ifdef CFG_MC_DIVIDE_ENABLED 9.48 if (divide_d == `TRUE) 9.49 - state <= #1 `LM32_MC_STATE_DIVIDE; 9.50 + state <= `LM32_MC_STATE_DIVIDE; 9.51 if (modulus_d == `TRUE) 9.52 - state <= #1 `LM32_MC_STATE_MODULUS; 9.53 + state <= `LM32_MC_STATE_MODULUS; 9.54 `endif 9.55 `ifdef CFG_MC_MULTIPLY_ENABLED 9.56 if (multiply_d == `TRUE) 9.57 - state <= #1 `LM32_MC_STATE_MULTIPLY; 9.58 + state <= `LM32_MC_STATE_MULTIPLY; 9.59 `endif 9.60 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.61 if (shift_left_d == `TRUE) 9.62 begin 9.63 - state <= #1 `LM32_MC_STATE_SHIFT_LEFT; 9.64 - sign_extend_x <= #1 sign_extend_d; 9.65 - cycles <= #1 operand_1_d[4:0]; 9.66 - a <= #1 operand_0_d; 9.67 - b <= #1 operand_0_d; 9.68 + state <= `LM32_MC_STATE_SHIFT_LEFT; 9.69 + sign_extend_x <= sign_extend_d; 9.70 + cycles <= operand_1_d[4:0]; 9.71 + a <= operand_0_d; 9.72 + b <= operand_0_d; 9.73 end 9.74 if (shift_right_d == `TRUE) 9.75 begin 9.76 - state <= #1 `LM32_MC_STATE_SHIFT_RIGHT; 9.77 - sign_extend_x <= #1 sign_extend_d; 9.78 - cycles <= #1 operand_1_d[4:0]; 9.79 - a <= #1 operand_0_d; 9.80 - b <= #1 operand_0_d; 9.81 + state <= `LM32_MC_STATE_SHIFT_RIGHT; 9.82 + sign_extend_x <= sign_extend_d; 9.83 + cycles <= operand_1_d[4:0]; 9.84 + a <= operand_0_d; 9.85 + b <= operand_0_d; 9.86 end 9.87 `endif 9.88 end 9.89 @@ -232,74 +232,74 @@ 9.90 begin 9.91 if (t[32] == 1'b0) 9.92 begin 9.93 - p <= #1 t[31:0]; 9.94 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.95 + p <= t[31:0]; 9.96 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.97 end 9.98 else 9.99 begin 9.100 - p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.101 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.102 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.103 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.104 end 9.105 - result_x <= #1 a; 9.106 + result_x <= a; 9.107 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.108 begin 9.109 // Check for divide by zero 9.110 - divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 9.111 - state <= #1 `LM32_MC_STATE_IDLE; 9.112 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 9.113 + state <= `LM32_MC_STATE_IDLE; 9.114 end 9.115 - cycles <= #1 cycles - 1'b1; 9.116 + cycles <= cycles - 1'b1; 9.117 end 9.118 `LM32_MC_STATE_MODULUS: 9.119 begin 9.120 if (t[32] == 1'b0) 9.121 begin 9.122 - p <= #1 t[31:0]; 9.123 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.124 + p <= t[31:0]; 9.125 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.126 end 9.127 else 9.128 begin 9.129 - p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.130 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.131 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.132 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.133 end 9.134 - result_x <= #1 p; 9.135 + result_x <= p; 9.136 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.137 begin 9.138 // Check for divide by zero 9.139 - divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 9.140 - state <= #1 `LM32_MC_STATE_IDLE; 9.141 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 9.142 + state <= `LM32_MC_STATE_IDLE; 9.143 end 9.144 - cycles <= #1 cycles - 1'b1; 9.145 + cycles <= cycles - 1'b1; 9.146 end 9.147 `endif 9.148 `ifdef CFG_MC_MULTIPLY_ENABLED 9.149 `LM32_MC_STATE_MULTIPLY: 9.150 begin 9.151 if (b[0] == 1'b1) 9.152 - p <= #1 p + a; 9.153 - b <= #1 {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 9.154 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.155 - result_x <= #1 p; 9.156 + p <= p + a; 9.157 + b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 9.158 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.159 + result_x <= p; 9.160 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.161 - state <= #1 `LM32_MC_STATE_IDLE; 9.162 - cycles <= #1 cycles - 1'b1; 9.163 + state <= `LM32_MC_STATE_IDLE; 9.164 + cycles <= cycles - 1'b1; 9.165 end 9.166 `endif 9.167 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.168 `LM32_MC_STATE_SHIFT_LEFT: 9.169 begin 9.170 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.171 - result_x <= #1 a; 9.172 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.173 + result_x <= a; 9.174 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.175 - state <= #1 `LM32_MC_STATE_IDLE; 9.176 - cycles <= #1 cycles - 1'b1; 9.177 + state <= `LM32_MC_STATE_IDLE; 9.178 + cycles <= cycles - 1'b1; 9.179 end 9.180 `LM32_MC_STATE_SHIFT_RIGHT: 9.181 begin 9.182 - b <= #1 {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 9.183 - result_x <= #1 b; 9.184 + b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 9.185 + result_x <= b; 9.186 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.187 - state <= #1 `LM32_MC_STATE_IDLE; 9.188 - cycles <= #1 cycles - 1'b1; 9.189 + state <= `LM32_MC_STATE_IDLE; 9.190 + cycles <= cycles - 1'b1; 9.191 end 9.192 `endif 9.193 endcase
10.1 --- a/lm32_monitor.v Sat Aug 06 00:02:46 2011 +0100 10.2 +++ b/lm32_monitor.v Sat Aug 06 01:26:56 2011 +0100 10.3 @@ -144,10 +144,10 @@ 10.4 begin 10.5 if (rst_i == `TRUE) 10.6 begin 10.7 - write_enable <= #1 `FALSE; 10.8 - MON_ACK_O <= #1 `FALSE; 10.9 - MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 10.10 - state <= #1 2'b00; 10.11 + write_enable <= `FALSE; 10.12 + MON_ACK_O <= `FALSE; 10.13 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 10.14 + state <= 2'b00; 10.15 end 10.16 else 10.17 begin 10.18 @@ -155,33 +155,33 @@ 10.19 2'b01: 10.20 begin 10.21 // Output read data to Wishbone 10.22 - MON_ACK_O <= #1 `TRUE; 10.23 - MON_DAT_O <= #1 data; 10.24 + MON_ACK_O <= `TRUE; 10.25 + MON_DAT_O <= data; 10.26 // Sub-word writes are performed using read-modify-write 10.27 // as the Lattice EBRs don't support byte enables 10.28 if (MON_WE_I == `TRUE) 10.29 - write_enable <= #1 `TRUE; 10.30 - write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 10.31 - write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 10.32 - write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 10.33 - write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 10.34 - state <= #1 2'b10; 10.35 + write_enable <= `TRUE; 10.36 + write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 10.37 + write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 10.38 + write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 10.39 + write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 10.40 + state <= 2'b10; 10.41 end 10.42 2'b10: 10.43 begin 10.44 // Wishbone access occurs in this cycle 10.45 - write_enable <= #1 `FALSE; 10.46 - MON_ACK_O <= #1 `FALSE; 10.47 - MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 10.48 - state <= #1 2'b00; 10.49 + write_enable <= `FALSE; 10.50 + MON_ACK_O <= `FALSE; 10.51 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 10.52 + state <= 2'b00; 10.53 end 10.54 default: 10.55 begin 10.56 - write_enable <= #1 `FALSE; 10.57 - MON_ACK_O <= #1 `FALSE; 10.58 + write_enable <= `FALSE; 10.59 + MON_ACK_O <= `FALSE; 10.60 // Wait for a Wishbone access 10.61 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 10.62 - state <= #1 2'b01; 10.63 + state <= 2'b01; 10.64 end 10.65 endcase 10.66 end
11.1 --- a/lm32_multiplier.v Sat Aug 06 00:02:46 2011 +0100 11.2 +++ b/lm32_multiplier.v Sat Aug 06 01:26:56 2011 +0100 11.3 @@ -99,21 +99,21 @@ 11.4 begin 11.5 if (rst_i == `TRUE) 11.6 begin 11.7 - muliplicand <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.8 - multiplier <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.9 - product <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.10 - result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.11 + muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 11.12 + multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 11.13 + product <= {`LM32_WORD_WIDTH{1'b0}}; 11.14 + result <= {`LM32_WORD_WIDTH{1'b0}}; 11.15 end 11.16 else 11.17 begin 11.18 if (stall_x == `FALSE) 11.19 begin 11.20 - muliplicand <= #1 operand_0; 11.21 - multiplier <= #1 operand_1; 11.22 + muliplicand <= operand_0; 11.23 + multiplier <= operand_1; 11.24 end 11.25 if (stall_m == `FALSE) 11.26 - product <= #1 muliplicand * multiplier; 11.27 - result <= #1 product; 11.28 + product <= muliplicand * multiplier; 11.29 + result <= product; 11.30 end 11.31 end 11.32
12.1 --- a/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 12.2 +++ b/lm32_ram.v Sat Aug 06 01:26:56 2011 +0100 12.3 @@ -191,13 +191,13 @@ 12.4 always @(posedge read_clk) 12.5 if (reset) 12.6 begin 12.7 - raw_data <= #1 0; 12.8 - raw <= #1 1'b0; 12.9 + raw_data <= 0; 12.10 + raw <= 1'b0; 12.11 end 12.12 else 12.13 begin 12.14 - raw_data <= #1 raw_data_nxt; 12.15 - raw <= #1 raw_nxt; 12.16 + raw_data <= raw_data_nxt; 12.17 + raw <= raw_nxt; 12.18 end 12.19 12.20 pmi_ram_dp_true 12.21 @@ -273,7 +273,7 @@ 12.22 12.23 always @(posedge read_clk) 12.24 if (enable_read) 12.25 - ra <= #1 read_address; 12.26 + ra <= read_address; 12.27 end 12.28 12.29 else 12.30 @@ -296,12 +296,12 @@ 12.31 // Write port 12.32 always @(posedge write_clk) 12.33 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 12.34 - mem[write_address] <= #1 write_data; 12.35 + mem[write_address] <= write_data; 12.36 12.37 // Register read address for use on next cycle 12.38 always @(posedge read_clk) 12.39 if (enable_read) 12.40 - ra <= #1 read_address; 12.41 + ra <= read_address; 12.42 12.43 end 12.44
13.1 --- a/lm32_shifter.v Sat Aug 06 00:02:46 2011 +0100 13.2 +++ b/lm32_shifter.v Sat Aug 06 01:26:56 2011 +0100 13.3 @@ -139,15 +139,15 @@ 13.4 begin 13.5 if (rst_i == `TRUE) 13.6 begin 13.7 - right_shift_result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 13.8 - direction_m <= #1 `FALSE; 13.9 + right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 13.10 + direction_m <= `FALSE; 13.11 end 13.12 else 13.13 begin 13.14 if (stall_x == `FALSE) 13.15 begin 13.16 - right_shift_result <= #1 {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 13.17 - direction_m <= #1 direction_x; 13.18 + right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 13.19 + direction_m <= direction_x; 13.20 end 13.21 end 13.22 end
14.1 --- a/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 14.2 +++ b/lm32_trace.v Sat Aug 06 01:26:56 2011 +0100 14.3 @@ -146,65 +146,65 @@ 14.4 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 14.5 14.6 initial begin 14.7 - trig_type <= #1 0; 14.8 - stop_type <= #1 0; 14.9 - trace_len <= #1 0; 14.10 - pc_low <= #1 0; 14.11 - pc_high <= #1 0; 14.12 - trace_start <= #1 0; 14.13 - trace_stop <= #1 0; 14.14 - ack_o <= #1 0; 14.15 - reg_dat_o <= #1 0; 14.16 - mem_valid <= #1 0; 14.17 - started <= #1 0; 14.18 - capturing <= #1 0; 14.19 + trig_type <= 0; 14.20 + stop_type <= 0; 14.21 + trace_len <= 0; 14.22 + pc_low <= 0; 14.23 + pc_high <= 0; 14.24 + trace_start <= 0; 14.25 + trace_stop <= 0; 14.26 + ack_o <= 0; 14.27 + reg_dat_o <= 0; 14.28 + mem_valid <= 0; 14.29 + started <= 0; 14.30 + capturing <= 0; 14.31 end 14.32 14.33 // the host side control 14.34 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.35 begin 14.36 if (rst_i == `TRUE) begin 14.37 - trig_type <= #1 0; 14.38 - trace_stop <= #1 0; 14.39 - trace_start <= #1 0; 14.40 - pc_low <= #1 0; 14.41 - pc_high <= #1 0; 14.42 - ack_o <= #1 0; 14.43 + trig_type <= 0; 14.44 + trace_stop <= 0; 14.45 + trace_start <= 0; 14.46 + pc_low <= 0; 14.47 + pc_high <= 0; 14.48 + ack_o <= 0; 14.49 end else begin 14.50 if (stb_i == `TRUE && ack_o == `FALSE) begin 14.51 if (rw_creg) begin // control register access 14.52 - ack_o <= #1 `TRUE; 14.53 + ack_o <= `TRUE; 14.54 if (we_i == `TRUE) begin 14.55 case ({adr_i[11:2],2'b0}) 14.56 // write to trig type 14.57 12'd0: 14.58 begin 14.59 if (sel_i[0]) begin 14.60 - trig_type[4:0] <= #1 dat_i[4:0]; 14.61 + trig_type[4:0] <= dat_i[4:0]; 14.62 end 14.63 if (sel_i[3]) begin 14.64 - trace_start <= #1 dat_i[31]; 14.65 - trace_stop <= #1 dat_i[30]; 14.66 + trace_start <= dat_i[31]; 14.67 + trace_stop <= dat_i[30]; 14.68 end 14.69 end 14.70 12'd8: 14.71 begin 14.72 - if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 14.73 - if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 14.74 - if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 14.75 - if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 14.76 + if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 14.77 + if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 14.78 + if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 14.79 + if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 14.80 end 14.81 12'd12: 14.82 begin 14.83 - if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 14.84 - if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 14.85 - if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 14.86 - if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 14.87 + if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 14.88 + if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 14.89 + if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 14.90 + if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 14.91 end 14.92 12'd16: 14.93 begin 14.94 if (sel_i[0])begin 14.95 - stop_type[4:0] <= #1 dat_i[4:0]; 14.96 + stop_type[4:0] <= dat_i[4:0]; 14.97 end 14.98 end 14.99 endcase 14.100 @@ -212,27 +212,27 @@ 14.101 case ({adr_i[11:2],2'b0}) 14.102 // read the trig type 14.103 12'd0: 14.104 - reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 14.105 + reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 14.106 12'd4: 14.107 - reg_dat_o <= #1 trace_len; 14.108 + reg_dat_o <= trace_len; 14.109 12'd8: 14.110 - reg_dat_o <= #1 pc_low; 14.111 + reg_dat_o <= pc_low; 14.112 12'd12: 14.113 - reg_dat_o <= #1 pc_high; 14.114 + reg_dat_o <= pc_high; 14.115 default: 14.116 - reg_dat_o <= #1 {27'b0,stop_type}; 14.117 + reg_dat_o <= {27'b0,stop_type}; 14.118 endcase 14.119 end // else: !if(we_i == `TRUE) 14.120 end else // read / write memory 14.121 if (we_i == `FALSE) begin 14.122 - ack_o <= #1 `TRUE; 14.123 + ack_o <= `TRUE; 14.124 end else 14.125 - ack_o <= #1 `FALSE; 14.126 + ack_o <= `FALSE; 14.127 // not allowed to write to trace memory 14.128 end else begin // if (stb_i == `TRUE) 14.129 - trace_start <= #1 `FALSE; 14.130 - trace_stop <= #1 `FALSE; 14.131 - ack_o <= #1 `FALSE; 14.132 + trace_start <= `FALSE; 14.133 + trace_stop <= `FALSE; 14.134 + ack_o <= `FALSE; 14.135 end // else: !if(stb_i == `TRUE) 14.136 end // else: !if(rst_i == `TRUE) 14.137 end 14.138 @@ -268,31 +268,31 @@ 14.139 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.140 begin 14.141 if (rst_i == `TRUE) begin 14.142 - tstate <= #1 0; 14.143 - trace_we <= #1 0; 14.144 - trace_len <= #1 0; 14.145 - ovrflw <= #1 `FALSE; 14.146 - mem_valid <= #1 0; 14.147 - started <= #1 0; 14.148 - capturing <= #1 0; 14.149 + tstate <= 0; 14.150 + trace_we <= 0; 14.151 + trace_len <= 0; 14.152 + ovrflw <= `FALSE; 14.153 + mem_valid <= 0; 14.154 + started <= 0; 14.155 + capturing <= 0; 14.156 end else begin 14.157 case (tstate) 14.158 3'd0: 14.159 // start capture 14.160 if (trace_start) begin 14.161 - tstate <= #1 3'd1; 14.162 - mem_valid <= #1 0; 14.163 - started <= #1 1; 14.164 + tstate <= 3'd1; 14.165 + mem_valid <= 0; 14.166 + started <= 1; 14.167 end 14.168 3'd1: 14.169 begin 14.170 // wait for trigger 14.171 if (trace_begin) begin 14.172 - capturing <= #1 1; 14.173 - tstate <= #1 3'd2; 14.174 - trace_we <= #1 `TRUE; 14.175 - trace_len <= #1 0; 14.176 - ovrflw <= #1 `FALSE; 14.177 + capturing <= 1; 14.178 + tstate <= 3'd2; 14.179 + trace_we <= `TRUE; 14.180 + trace_len <= 0; 14.181 + ovrflw <= `FALSE; 14.182 end 14.183 end // case: 3'd1 14.184 14.185 @@ -300,18 +300,18 @@ 14.186 begin 14.187 if (trace_pc_valid) begin 14.188 if (trace_len[mem_addr_width]) 14.189 - trace_len <= #1 0; 14.190 + trace_len <= 0; 14.191 else 14.192 - trace_len <= #1 trace_len + 1; 14.193 + trace_len <= trace_len + 1; 14.194 end 14.195 - if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 14.196 + if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 14.197 // wait for stop condition 14.198 if (trace_end) begin 14.199 - tstate <= #1 3'd0; 14.200 - trace_we <= #1 0; 14.201 - mem_valid <= #1 1; 14.202 - started <= #1 0; 14.203 - capturing <= #1 0; 14.204 + tstate <= 3'd0; 14.205 + trace_we <= 0; 14.206 + mem_valid <= 1; 14.207 + started <= 0; 14.208 + capturing <= 0; 14.209 end 14.210 end // case: 3'd2 14.211 endcase
15.1 --- a/typea.v Sat Aug 06 00:02:46 2011 +0100 15.2 +++ b/typea.v Sat Aug 06 01:26:56 2011 +0100 15.3 @@ -80,13 +80,13 @@ 15.4 always @ (negedge CLK or negedge RESET_N) 15.5 begin 15.6 if (RESET_N == 1'b0) 15.7 - tdoInt <= #1 1'b0; 15.8 + tdoInt <= 1'b0; 15.9 else if (CLK == 1'b0) 15.10 if (CLKEN == 1'b1) 15.11 if (CAPTURE_DR == 1'b0) 15.12 - tdoInt <= #1 TDI; 15.13 + tdoInt <= TDI; 15.14 else 15.15 - tdoInt <= #1 DATA_IN; 15.16 + tdoInt <= DATA_IN; 15.17 end 15.18 15.19 assign TDO = tdoInt; 15.20 @@ -94,9 +94,9 @@ 15.21 always @ (negedge CLK or negedge RESET_N) 15.22 begin 15.23 if (RESET_N == 1'b0) 15.24 - DATA_OUT <= #1 1'b0; 15.25 + DATA_OUT <= 1'b0; 15.26 else if (CLK == 1'b0) 15.27 if (UPDATE_DR == 1'b1) 15.28 - DATA_OUT <= #1 tdoInt; 15.29 + DATA_OUT <= tdoInt; 15.30 end 15.31 endmodule
16.1 --- a/typeb.v Sat Aug 06 00:02:46 2011 +0100 16.2 +++ b/typeb.v Sat Aug 06 01:26:56 2011 +0100 16.3 @@ -64,13 +64,13 @@ 16.4 always @ (negedge CLK or negedge RESET_N) 16.5 begin 16.6 if (RESET_N== 1'b0) 16.7 - tdoInt <= #1 1'b0; 16.8 + tdoInt <= 1'b0; 16.9 else if (CLK == 1'b0) 16.10 if (CLKEN==1'b1) 16.11 if (CAPTURE_DR==1'b0) 16.12 - tdoInt <= #1 TDI; 16.13 + tdoInt <= TDI; 16.14 else 16.15 - tdoInt <= #1 DATA_IN; 16.16 + tdoInt <= DATA_IN; 16.17 end 16.18 16.19 assign TDO = tdoInt;