1.1 diff -r 11aef665a5d8 -r 522426d22baa document/dma.htm 1.2 --- a/document/dma.htm Fri Aug 13 10:43:05 2010 +0100 1.3 +++ b/document/dma.htm Sat Aug 06 01:48:48 2011 +0100 1.4 @@ -111,9 +111,9 @@ 1.5 writeIntopicBar(4); 1.6 //--> 1.7 </script> 1.8 -<h1>LatticeMico32 DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 1.9 +<h1>LatticeMico DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 1.10 1.11 -<p>The LatticeMico32 direct memory access controller (DMA) provides a master 1.12 +<p>The LatticeMico direct memory access controller (DMA) provides a master 1.13 read port, a master write port, and a slave port to control data transmission. 1.14 </p> 1.15 1.16 @@ -140,6 +140,23 @@ 1.17 <tr valign="top" class="whs6"> 1.18 <td colspan="1" rowspan="1" width="86px" class="whs9"> 1.19 <p class=Table 1.20 + style="font-weight: normal;">3.3</td> 1.21 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 1.22 +<p class=Table>Added software support for LatticeMico8.</td></tr> 1.23 + 1.24 +<tr valign="top" class="whs6"> 1.25 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 1.26 +<p class=Table 1.27 + style="font-weight: normal;">3.2 (8.1 SP1)</td> 1.28 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 1.29 +<p class=Table>The data busses on the three WISHBONE interfaces can be 1.30 + configured to be 8 or 32 bits. Support added for handling WISHBONE RTY 1.31 + (retry) for burst transfers. Support added for handling WISHBONE ERR (error). 1.32 + Register map updated to support 8-bit and 32-bit WISHBONE data bus.</td></tr> 1.33 + 1.34 +<tr valign="top" class="whs6"> 1.35 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 1.36 +<p class=Table 1.37 style="font-weight: normal;">3.1 (8.0)</td> 1.38 <td colspan="1" rowspan="1" width="504px" class="whs10"> 1.39 <p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone 1.40 @@ -176,9 +193,6 @@ 1.41 <h2>Dialog Box Parameters</h2> 1.42 1.43 <table x-use-null-cells cellspacing="0" class="whs12"> 1.44 -<script language='JavaScript'><!-- 1.45 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 1.46 -//--></script> 1.47 <col> 1.48 <col> 1.49 1.50 @@ -218,16 +232,34 @@ 1.51 <tr valign="top" class="whs13"> 1.52 <td colspan="1" rowspan="1" class="whs18"> 1.53 <p class=Table 1.54 - style="margin-right: 2px;">Length Width</td> 1.55 + style="margin-right: 2px;">Retry Timeout</p> 1.56 +<p class=table> </td> 1.57 <td colspan="1" rowspan="1" class="whs19"> 1.58 -<p class=Table>Specifies the number of bits in the length register. The 1.59 - length register holds a count value that determines the number of DMA 1.60 - transactions to be performed. Supported values are 1 to 32. The default 1.61 - is 16. The default value permits up to 65535 (0XFFFF) memory transactions 1.62 - to be performed.</td></tr> 1.63 -<script language='JavaScript'><!-- 1.64 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 1.65 -//--></script> 1.66 +<p class=Table>Specifies the number of WISHBONE clock cycles that the DMA 1.67 + controller must wait after the source or destination asserts the WISHBONE 1.68 + RTY before retrying the same WISHBONE cycle. Supported 1.69 + values are 1 to 255. The default is 16. </p> 1.70 +<p class=table> </td></tr> 1.71 + 1.72 +<tr valign="top" class="whs13"> 1.73 +<td colspan="2" rowspan="1" class="whs18"> 1.74 +<p class=Table 1.75 + style="font-weight: bold;">WISHBONE Configuration</td> 1.76 +</tr> 1.77 + 1.78 +<tr valign="top" class="whs13"> 1.79 +<td colspan="1" rowspan="1" class="whs18"> 1.80 +<p class=Table>Control Port Data Bus Width</td> 1.81 +<td colspan="1" rowspan="1" class="whs19"> 1.82 +<p class=Table>Configures the control port's WISHBONE data bus to be 8 1.83 + or 32 bits wide.</td></tr> 1.84 + 1.85 +<tr valign="top" class="whs13"> 1.86 +<td colspan="1" rowspan="1" class="whs18"> 1.87 +<p class=Table>Read/Write Port Data Bus Width</td> 1.88 +<td colspan="1" rowspan="1" class="whs19"> 1.89 +<p class=Table>Configures the read and write WISHBONE master port data 1.90 + buses to be 8 or 32 bits wide.</td></tr> 1.91 </table> 1.92 1.93