1.1 diff -r 000000000000 -r 11aef665a5d8 rtl/verilog/wb_dma_ctrl.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/rtl/verilog/wb_dma_ctrl.v Fri Aug 13 10:43:05 2010 +0100 1.4 @@ -0,0 +1,237 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LM32 DMA Component 1.22 +// File : wb_dma_ctrl.v 1.23 +// Title : DMA controller top file 1.24 +// Dependencies : None 1.25 +// Version : 7.0 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// 1. Read and Write channel of DMA controller are working in parallel, 1.29 +// due to that now as soon as FIFO is not empty write channel of the DMA 1.30 +// controller start writing data to the slave. 1.31 +// 2. Burst Size supported by DMA controller is increased to support bigger 1.32 +// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.33 +// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.34 +// For this Burst Size field of the control register is increased to 2 bits. 1.35 +// 3. Glitch is removed on the S_ACK_O signal. 1.36 +// Version : 3.1 1.37 +// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.38 +// : which defines alignement of bytes in sub-word transfers. 1.39 +// ============================================================================= 1.40 + 1.41 +`ifndef WB_DMA_CTRL_FILE 1.42 +`define WB_DMA_CTRL_FILE 1.43 +`include "system_conf.v" 1.44 +module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16, 1.45 + parameter FIFO_IMPLEMENTATION = "EBR") 1.46 +( 1.47 + //master read port 1.48 + MA_ADR_O, //32bits 1.49 + MA_WE_O, 1.50 + MA_SEL_O, //4bits 1.51 + MA_STB_O, 1.52 + MA_CYC_O, 1.53 + MA_LOCK_O, 1.54 + MA_CTI_O, 1.55 + MA_BTE_O, 1.56 + MA_DAT_I, //32bits 1.57 + MA_DAT_O, //32bits 1.58 + MA_ACK_I, 1.59 + MA_ERR_I, 1.60 + MA_RTY_I, 1.61 + //master write port 1.62 + MB_ADR_O, //32bits 1.63 + MB_DAT_O, //32bits 1.64 + MB_WE_O, 1.65 + MB_SEL_O, //4bits 1.66 + MB_STB_O, 1.67 + MB_CYC_O, 1.68 + MB_LOCK_O, 1.69 + MB_CTI_O, 1.70 + MB_BTE_O, 1.71 + MB_DAT_I, //32bits 1.72 + MB_ACK_I, 1.73 + MB_ERR_I, 1.74 + MB_RTY_I, 1.75 + //slave port 1.76 + S_ADR_I, //32bits 1.77 + S_DAT_I, //32bits 1.78 + S_WE_I, 1.79 + S_STB_I, 1.80 + S_CYC_I, 1.81 + S_SEL_I, 1.82 + S_LOCK_I, 1.83 + S_CTI_I, 1.84 + S_BTE_I, 1.85 + S_DAT_O, //32bits 1.86 + S_ACK_O, 1.87 + S_ERR_O, 1.88 + S_RTY_O, 1.89 + S_INT_O, 1.90 + //system clock and reset 1.91 + CLK_I, 1.92 + RST_I 1.93 + ); 1.94 + //master read port 1.95 + output [31:0] MA_ADR_O; //32bits 1.96 + output MA_WE_O; 1.97 + output [3:0] MA_SEL_O; //4bits 1.98 + output MA_STB_O; 1.99 + output MA_CYC_O; 1.100 + output MA_LOCK_O; 1.101 + output [2:0] MA_CTI_O; 1.102 + output [1:0] MA_BTE_O; 1.103 + output [31:0] MA_DAT_O; //32bits 1.104 + input [31:0] MA_DAT_I; //32bits 1.105 + input MA_ACK_I; 1.106 + input MA_ERR_I; 1.107 + input MA_RTY_I; 1.108 + //master write port 1.109 + output [31:0] MB_ADR_O; //32bits 1.110 + output [31:0] MB_DAT_O; //32bits 1.111 + output MB_WE_O; 1.112 + output [3:0] MB_SEL_O; //4bits 1.113 + output MB_STB_O; 1.114 + output MB_CYC_O; 1.115 + output [2:0] MB_CTI_O; 1.116 + output MB_LOCK_O; 1.117 + output [1:0] MB_BTE_O; 1.118 + input [31:0] MB_DAT_I; //32bits 1.119 + input MB_ACK_I; 1.120 + input MB_ERR_I; 1.121 + input MB_RTY_I; 1.122 + //slave port 1.123 + input [31:0] S_ADR_I; //32bits 1.124 + input [31:0] S_DAT_I; //32bits 1.125 + input S_WE_I; 1.126 + input S_STB_I; 1.127 + input S_CYC_I; 1.128 + input [2:0] S_CTI_I; 1.129 + input [1:0] S_BTE_I; 1.130 + input [3:0] S_SEL_I; 1.131 + input S_LOCK_I; 1.132 + output [31:0] S_DAT_O; //32bits 1.133 + output S_ACK_O; 1.134 + output S_ERR_O; 1.135 + output S_RTY_O; 1.136 + output S_INT_O; 1.137 + //system clock and reset 1.138 + input CLK_I; 1.139 + input RST_I; 1.140 + 1.141 + wire [31:0] MA_DAT_O = 0; 1.142 + wire [1:0] MA_BTE_O = 0; 1.143 + wire MA_LOCK_O; 1.144 + 1.145 + wire [1:0] MB_BTE_O = 0; 1.146 + wire MB_LOCK_O; 1.147 + 1.148 + wire S_ERR_O = 0; 1.149 + wire S_RTY_O = 0; 1.150 + 1.151 + wire [LENGTH_WIDTH-1:0] data_length;//read back data 1.152 + wire [2:0] incr_unit; 1.153 + wire [31:0] reg_00_data; 1.154 + wire [31:0] reg_04_data; 1.155 + wire [3:0] M_SEL_O; 1.156 + 1.157 + //slave port:master write/read data to/from register file. 1.158 + SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH), 1.159 + .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG( 1.160 + .S_ADR_I (S_ADR_I ), 1.161 + .S_DAT_I (S_DAT_I ), 1.162 + .S_WE_I (S_WE_I ), 1.163 + .S_STB_I (S_STB_I ), 1.164 + .S_CYC_I (S_CYC_I ), 1.165 + .S_CTI_I (S_CTI_I ), 1.166 + .S_DAT_O (S_DAT_O ), 1.167 + .S_ACK_O (S_ACK_O ), 1.168 + .S_INT_O (S_INT_O ), 1.169 + //Master Addr 1.170 + .M_SEL_O (M_SEL_O ), 1.171 +// .MA_SEL_O (MA_SEL_O ), 1.172 +// .MB_SEL_O (MB_SEL_O ), 1.173 + //internal signals 1.174 + .reg_start (reg_start ), 1.175 + .reg_status (reg_status ), 1.176 + .reg_interrupt (reg_interrupt ), 1.177 + .reg_busy (reg_busy ), 1.178 + .data_length (data_length ), 1.179 + .reg_cntlg (reg_cntlg ), 1.180 + .reg_bt2 (reg_bt2 ), 1.181 + .reg_bt1 (reg_bt1 ), 1.182 + .reg_bt0 (reg_bt0 ), 1.183 + .reg_s_con (reg_s_con ), 1.184 + .reg_d_con (reg_d_con ), 1.185 + .incr_unit (incr_unit ), 1.186 + .reg_00_data (reg_00_data ), 1.187 + .reg_04_data (reg_04_data ), 1.188 + //system clock and reset 1.189 + .CLK_I (CLK_I ), 1.190 + .RST_I (RST_I ) 1.191 + ); 1.192 + 1.193 + //Master control 1.194 + MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH), 1.195 + .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL( 1.196 + //master read port 1.197 + .MA_ADR_O (MA_ADR_O ), 1.198 + .MA_SEL_O (MA_SEL_O ), 1.199 + .MA_WE_O (MA_WE_O ), 1.200 + .MA_STB_O (MA_STB_O ), 1.201 + .MA_CYC_O (MA_CYC_O ), 1.202 + .MA_CTI_O (MA_CTI_O ), 1.203 + .MA_LOCK_O (MA_LOCK_O ), 1.204 + .MA_DAT_I (MA_DAT_I ), //32bits 1.205 + .MA_ACK_I (MA_ACK_I ), 1.206 + .MA_ERR_I (MA_ERR_I ), 1.207 + .MA_RTY_I (MA_RTY_I ), 1.208 + //master write port 1.209 + .MB_ADR_O (MB_ADR_O ), 1.210 + .MB_SEL_O (MB_SEL_O ), 1.211 + .MB_DAT_O (MB_DAT_O ), //32bits 1.212 + .MB_WE_O (MB_WE_O ), 1.213 + .MB_STB_O (MB_STB_O ), 1.214 + .MB_CYC_O (MB_CYC_O ), 1.215 + .MB_CTI_O (MB_CTI_O ), 1.216 + .MB_LOCK_O (MB_LOCK_O ), 1.217 + .MB_ACK_I (MB_ACK_I ), 1.218 + .MB_ERR_I (MB_ERR_I ), 1.219 + .MB_RTY_I (MB_RTY_I ), 1.220 + //register interface 1.221 + .M_SEL_O (M_SEL_O ), 1.222 + .reg_start (reg_start ), 1.223 + .reg_status (reg_status ), 1.224 + .reg_interrupt (reg_interrupt ), 1.225 + .reg_busy (reg_busy ), 1.226 + .data_length (data_length ), 1.227 + .reg_cntlg (reg_cntlg ), 1.228 + .reg_bt2 (reg_bt2 ), 1.229 + .reg_bt1 (reg_bt1 ), 1.230 + .reg_bt0 (reg_bt0 ), 1.231 + .reg_s_con (reg_s_con ), 1.232 + .reg_d_con (reg_d_con ), 1.233 + .incr_unit (incr_unit ), 1.234 + .reg_00_data (reg_00_data ), 1.235 + .reg_04_data (reg_04_data ), 1.236 + //system clock and reset 1.237 + .CLK_I (CLK_I ), 1.238 + .RST_I (RST_I ) 1.239 + ); 1.240 +endmodule // WB_DMA_CTRL 1.241 +`endif // WB_DMA_CTRL_FILE