Sat, 06 Aug 2011 01:48:48 +0100
Update to LM32 DMA v3.3
+// Version : 3.2
+// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
+// : Read/Write Ports can be independently configured.
+// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
+// : retry results in the current burst or classic cycle
+// : being issued again after a retry timeout.
+// : 3. Support for "error" on receipt of a WISHBONE ERR. This
+// : results in the current dma transfer being terminated
+// : and the error is updated within the STATUS CSR.
+// : 4. Support for burst size of 64.
+// :
+// Version : 3.3
+// : Support for MachXO2 added. The MachXO2 only has a FIFO
+// : with separate read/write clocks.
1.1 diff -r 11aef665a5d8 -r 522426d22baa dma.xml 1.2 --- a/dma.xml Fri Aug 13 10:43:05 2010 +0100 1.3 +++ b/dma.xml Sat Aug 06 01:48:48 2011 +0100 1.4 @@ -1,9 +1,9 @@ 1.5 <?xml version="1.0" encoding="UTF-8"?> 1.6 -<Component Name="wb_dma_ctrl" Text="DMA" Type="IO" Ver="3.1" Help="wb_dma_ctrl\document\dma.htm"> 1.7 +<Component Name="wb_dma_ctrl" Text="DMA" Type="IO" Ver="3.3" Help="wb_dma_ctrl\document\dma.htm" Processor="LM32,LM8" LatticeFamily="All" Device="All"> 1.8 <MasterSlavePorts> 1.9 - <MasterPort Prefix="MA" Name="Read Master Port" Type="DMAR" Priority="2" /> 1.10 - <MasterPort Prefix="MB" Name="Write Master Port" Type="DMAW" Priority="3"/> 1.11 - <SlavePort Prefix="S" Name="Control Port" Type="DATA"/> 1.12 + <MasterPort Prefix="MA" Port="MA" Name="Read Master Port" Type="DMAR" Priority="2"/> 1.13 + <MasterPort Prefix="MB" Port="MB" Name="Write Master Port" Type="DMAW" Priority="3"/> 1.14 + <SlavePort Prefix="S" Port="S" Name="Control Port" Type="DATA"/> 1.15 </MasterSlavePorts> 1.16 <ClockPort Name="CLK_I " Description="Clock one"/> 1.17 <ResetPort Name="RST_I " Description="Reset"/> 1.18 @@ -14,18 +14,24 @@ 1.19 <File Name="../components/wb_dma_ctrl/rtl/verilog/wb_dma_ctrl.v" /> 1.20 </Files> 1.21 <DeviceDriver InitRoutine="MicoDMAInit" StructName="MicoDMACtx_t"> 1.22 - <DDInclude Include="LookupServices.h"/> 1.23 + <DDInclude Include="LookupServices.h" Processor="LM32"/> 1.24 + <DDInclude Include="stddef.h" Processor="LM8"/> 1.25 + <DDIRQ IRQAPI="MicoDMAISR" Parameter="InstanceName" Include="MicoDMA.h" Processor="LM8"/> 1.26 + <DDPreProcessor Name="__MICODMA_USER_IRQ_HANDLER__" Processor="LM8"/> 1.27 <DDstruct> 1.28 - <DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string"/> 1.29 - <DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" /> 1.30 - <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type = "uninitialized" Value=""/> 1.31 - <DDSElem MemberName = "irq" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" /> 1.32 - <DDSElem MemberName = "maxLength" MemberType = "unsigned int" Type = "Parm" Value = "LENGTH_WIDTH" /> 1.33 - <DDSElem MemberName = "flags" MemberType = "unsigned int" Type = "uninitialized" Value = "" /> 1.34 - <DDSElem MemberName = "pCurr" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.35 - <DDSElem MemberName = "pHead" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.36 - <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.37 - <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.38 + <DDSElem MemberName="name" MemberType="const char*" Type = "Parm" Value="InstanceName" Format="string" Processor="LM32,LM8"/> 1.39 + <DDSElem MemberName="base" MemberType="unsigned int" Type="Parm" Value="BASE_ADDRESS" Port="S" Processor="LM32"/> 1.40 + <DDSElem MemberName="base" MemberType="size_t" Type="Parm" Value="BASE_ADDRESS" Port="S" Processor="LM8"/> 1.41 + <DDSElem MemberName="wb" MemberType="unsigned char" Type="Parm" Value="WB_DAT_WIDTH" Port="S"/> 1.42 + <DDSElem MemberName="lookupReg" MemberType="DeviceReg_t" Type="uninitialized" Value="" Processor="LM32"/> 1.43 + <DDSElem MemberName="irq" MemberType="unsigned int" Type="Interrupt" Value="IRQ_LEVEL" Processor="LM32"/> 1.44 + <DDSElem MemberName="irq" MemberType="unsigned char" Type="Interrupt" Value="IRQ_LEVEL" Processor="LM8"/> 1.45 + <DDSElem MemberName="maxLength" MemberType="unsigned int" Type="Parm" Value="LENGTH_WIDTH" Processor="LM32"/> 1.46 + <DDSElem MemberName="flags" MemberType="unsigned int" Type="uninitialized" Value="" Processor="LM32"/> 1.47 + <DDSElem MemberName="pCurr" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.48 + <DDSElem MemberName="pHead" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.49 + <DDSElem MemberName="prev" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.50 + <DDSElem MemberName="next" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.51 </DDstruct> 1.52 </DeviceDriver> 1.53 <PMIDef> 1.54 @@ -33,20 +39,30 @@ 1.55 <Module Name="pmi_fifo_dc" /> 1.56 </PMIDef> 1.57 <Parms> 1.58 - <Parm Name="InstanceName" Value="dma" Type="string" isiname="true" Text="Instance Name"/> 1.59 - <Parm Name="BASE_ADDRESS" Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/> 1.60 - <Parm Name="FIFO_IMPLEMENTATION" Value="EBR" Type="String" ListValues="EBR,LUT" Text="FIFO Implementation" isparm="true"/> 1.61 - <Parm Name="SIZE" Value="128" Type="Integer" issize="true" Text="Size" Enable="false"/> 1.62 - <Parm Name="DISABLE" Type="define" Value="undef" isdisable="true" Text="Disable Component"/> 1.63 - <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address "/> 1.64 - <Parm Name="LENGTH_WIDTH" Value="16" Type="Integer" ValueRange="1-32" Text="Length Width" isparm="true"/> 1.65 + <Parm Name="InstanceName" Value="dma" Type="string" isiname="true" Text="Instance Name"/> 1.66 + <Parm Name="BASE_ADDRESS" Port="S" Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/> 1.67 + <Parm Name="FIFO_IMPLEMENTATION" Value="EBR" Type="String" ListValues="EBR,LUT" Text="FIFO Implementation" isparm="true"/> 1.68 + <Parm Name="SIZE" Port="S" Value="128" Type="Integer" issize="true" Text="Size" Enable="false"/> 1.69 + <Parm Name="DISABLE" Value="undef" Type="define" isdisable="true" Text="Disable Component"/> 1.70 + <Parm Name="ADDRESS_LOCK" Value="undef" Type="Define" Text="Lock Address "/> 1.71 + <Parm Name="RETRY_TIMEOUT" Value="16" Type="Integer" ValueRange="1-255" Text="Retry Timeout" isparm="true"/> 1.72 + <Parm Name="LENGTH_WIDTH" Value="32" Type="Integer" ValueRange="1-32" Text="Length Width" isparm="false"/> 1.73 + <Parm Name="WB_DAT_WIDTH" Port="S" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="Control Port Data Bus Width" isparm="true"/> 1.74 + <Parm Name="WB_ADR_WIDTH" Port="S" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.75 + <Parm Name="WB_DAT_WIDTH" Port="MA" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="Read/Write Ports Data Bus Width" isparm="true" SetValTo="MB"/> 1.76 + <Parm Name="WB_ADR_WIDTH" Port="MA" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.77 + <Parm Name="WB_DAT_WIDTH" Port="MB" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="WISHBONE Data Bus Width" isparm="true"/> 1.78 + <Parm Name="WB_ADR_WIDTH" Port="MB" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.79 </Parms> 1.80 <GUIS Columns="2" Help="document\dma.htm" Name="WB_DMA_CTRL"> 1.81 <GUI Widget="Text" Span="1" Name="InstanceName" Width="40"/> 1.82 - <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/> 1.83 + <GUI Widget="Text" Span="1" Name="BASE_ADDRESS" Port="S"/> 1.84 <GUI Widget="Combo" Span="1" Name="FIFO_IMPLEMENTATION"/> 1.85 <GUI Widget="Group" Span="2" Name="SETTINGS" Text="Settings" Columns="3"/> 1.86 <GUI Widget="Label" Span="1" Name=""/> 1.87 - <GUI Widget="Spinner" Span="1" Name="LENGTH_WIDTH"/> 1.88 + <GUI Widget="Spinner" Span="1" Name="RETRY_TIMEOUT"/> 1.89 + <GUI Widget="Group" Span="2" Text="WISHBONE Configuration" Columns="2"/> 1.90 + <GUI Widget="Combo" Span="1" Name="WB_DAT_WIDTH" Port="S"/> 1.91 + <GUI Widget="Combo" Span="1" Name="WB_DAT_WIDTH" Port="MA"/> 1.92 </GUIS> 1.93 </Component>
2.1 diff -r 11aef665a5d8 -r 522426d22baa document/dma.htm 2.2 --- a/document/dma.htm Fri Aug 13 10:43:05 2010 +0100 2.3 +++ b/document/dma.htm Sat Aug 06 01:48:48 2011 +0100 2.4 @@ -111,9 +111,9 @@ 2.5 writeIntopicBar(4); 2.6 //--> 2.7 </script> 2.8 -<h1>LatticeMico32 DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 2.9 +<h1>LatticeMico DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 2.10 2.11 -<p>The LatticeMico32 direct memory access controller (DMA) provides a master 2.12 +<p>The LatticeMico direct memory access controller (DMA) provides a master 2.13 read port, a master write port, and a slave port to control data transmission. 2.14 </p> 2.15 2.16 @@ -140,6 +140,23 @@ 2.17 <tr valign="top" class="whs6"> 2.18 <td colspan="1" rowspan="1" width="86px" class="whs9"> 2.19 <p class=Table 2.20 + style="font-weight: normal;">3.3</td> 2.21 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 2.22 +<p class=Table>Added software support for LatticeMico8.</td></tr> 2.23 + 2.24 +<tr valign="top" class="whs6"> 2.25 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 2.26 +<p class=Table 2.27 + style="font-weight: normal;">3.2 (8.1 SP1)</td> 2.28 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 2.29 +<p class=Table>The data busses on the three WISHBONE interfaces can be 2.30 + configured to be 8 or 32 bits. Support added for handling WISHBONE RTY 2.31 + (retry) for burst transfers. Support added for handling WISHBONE ERR (error). 2.32 + Register map updated to support 8-bit and 32-bit WISHBONE data bus.</td></tr> 2.33 + 2.34 +<tr valign="top" class="whs6"> 2.35 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 2.36 +<p class=Table 2.37 style="font-weight: normal;">3.1 (8.0)</td> 2.38 <td colspan="1" rowspan="1" width="504px" class="whs10"> 2.39 <p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone 2.40 @@ -176,9 +193,6 @@ 2.41 <h2>Dialog Box Parameters</h2> 2.42 2.43 <table x-use-null-cells cellspacing="0" class="whs12"> 2.44 -<script language='JavaScript'><!-- 2.45 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 2.46 -//--></script> 2.47 <col> 2.48 <col> 2.49 2.50 @@ -218,16 +232,34 @@ 2.51 <tr valign="top" class="whs13"> 2.52 <td colspan="1" rowspan="1" class="whs18"> 2.53 <p class=Table 2.54 - style="margin-right: 2px;">Length Width</td> 2.55 + style="margin-right: 2px;">Retry Timeout</p> 2.56 +<p class=table> </td> 2.57 <td colspan="1" rowspan="1" class="whs19"> 2.58 -<p class=Table>Specifies the number of bits in the length register. The 2.59 - length register holds a count value that determines the number of DMA 2.60 - transactions to be performed. Supported values are 1 to 32. The default 2.61 - is 16. The default value permits up to 65535 (0XFFFF) memory transactions 2.62 - to be performed.</td></tr> 2.63 -<script language='JavaScript'><!-- 2.64 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 2.65 -//--></script> 2.66 +<p class=Table>Specifies the number of WISHBONE clock cycles that the DMA 2.67 + controller must wait after the source or destination asserts the WISHBONE 2.68 + RTY before retrying the same WISHBONE cycle. Supported 2.69 + values are 1 to 255. The default is 16. </p> 2.70 +<p class=table> </td></tr> 2.71 + 2.72 +<tr valign="top" class="whs13"> 2.73 +<td colspan="2" rowspan="1" class="whs18"> 2.74 +<p class=Table 2.75 + style="font-weight: bold;">WISHBONE Configuration</td> 2.76 +</tr> 2.77 + 2.78 +<tr valign="top" class="whs13"> 2.79 +<td colspan="1" rowspan="1" class="whs18"> 2.80 +<p class=Table>Control Port Data Bus Width</td> 2.81 +<td colspan="1" rowspan="1" class="whs19"> 2.82 +<p class=Table>Configures the control port's WISHBONE data bus to be 8 2.83 + or 32 bits wide.</td></tr> 2.84 + 2.85 +<tr valign="top" class="whs13"> 2.86 +<td colspan="1" rowspan="1" class="whs18"> 2.87 +<p class=Table>Read/Write Port Data Bus Width</td> 2.88 +<td colspan="1" rowspan="1" class="whs19"> 2.89 +<p class=Table>Configures the read and write WISHBONE master port data 2.90 + buses to be 8 or 32 bits wide.</td></tr> 2.91 </table> 2.92 2.93
3.1 diff -r 11aef665a5d8 -r 522426d22baa document/dma.pdf 3.2 Binary file document/dma.pdf has changed
4.1 diff -r 11aef665a5d8 -r 522426d22baa drivers/peripheral.mk 4.2 --- a/drivers/peripheral.mk Fri Aug 13 10:43:05 2010 +0100 4.3 +++ b/drivers/peripheral.mk Sat Aug 06 01:48:48 2011 +0100 4.4 @@ -2,8 +2,7 @@ 4.5 # Identify source-paths for this device's driver-sources, 4.6 # compiled when building the library 4.7 #--------------------------------------------------------- 4.8 -LIBRARY_C_SRCS += MicoDMA.c \ 4.9 - MicoDMAService.c 4.10 +LIBRARY_C_SRCS += 4.11 LIBRARY_ASM_SRCS += 4.12 4.13
5.1 diff -r 11aef665a5d8 -r 522426d22baa rtl/verilog/master_ctrl.v 5.2 --- a/rtl/verilog/master_ctrl.v Fri Aug 13 10:43:05 2010 +0100 5.3 +++ b/rtl/verilog/master_ctrl.v Sat Aug 06 01:48:48 2011 +0100 5.4 @@ -1,1188 +1,902 @@ 5.5 -// ============================================================================= 5.6 -// COPYRIGHT NOTICE 5.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 5.8 -// ALL RIGHTS RESERVED 5.9 -// This confidential and proprietary software may be used only as authorised by 5.10 -// a licensing agreement from Lattice Semiconductor Corporation. 5.11 -// The entire notice above must be reproduced on all authorized copies and 5.12 -// copies may only be made to the extent permitted by a licensing agreement from 5.13 -// Lattice Semiconductor Corporation. 5.14 +// ================================================================== 5.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 5.16 +// ------------------------------------------------------------------ 5.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 5.18 +// ALL RIGHTS RESERVED 5.19 +// ------------------------------------------------------------------ 5.20 +// 5.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 5.22 +// 5.23 +// Permission: 5.24 +// 5.25 +// Lattice Semiconductor grants permission to use this code 5.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 5.27 +// Open Source License Agreement. 5.28 +// 5.29 +// Disclaimer: 5.30 // 5.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 5.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 5.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 5.34 -// U.S.A email: techsupport@latticesemi.com 5.35 -// =============================================================================/ 5.36 +// Lattice Semiconductor provides no warranty regarding the use or 5.37 +// functionality of this code. It is the user's responsibility to 5.38 +// verify the user’s design for consistency and functionality through 5.39 +// the use of formal verification methods. 5.40 +// 5.41 +// -------------------------------------------------------------------- 5.42 +// 5.43 +// Lattice Semiconductor Corporation 5.44 +// 5555 NE Moore Court 5.45 +// Hillsboro, OR 97214 5.46 +// U.S.A 5.47 +// 5.48 +// TEL: 1-800-Lattice (USA and Canada) 5.49 +// 503-286-8001 (other locations) 5.50 +// 5.51 +// web: http://www.latticesemi.com/ 5.52 +// email: techsupport@latticesemi.com 5.53 +// 5.54 +// -------------------------------------------------------------------- 5.55 // FILE DETAILS 5.56 // Project : LM32 DMA Component 5.57 -// File : master_ctrl.v 5.58 -// Title : DMA Master controller 5.59 +// File : wb_dma_ctrl.v 5.60 +// Title : DMA controller top file 5.61 // Dependencies : None 5.62 -// 5.63 -// Version 3.1 5.64 -// 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 5.65 -// alignement of bytes in sub-word transfers. 5.66 -// 2. Removed glitch that did not pause the burst write when the read burst 5.67 -// was paused by the "read slave". 5.68 -// 5.69 -// Version 7.0SP2, 3.0 5.70 -// 1. Read and Write channel of DMA controller are working in parallel, 5.71 -// due to that now as soon as FIFO is not empty write channel of the DMA 5.72 -// controller start writing data to the slave. 5.73 -// 2. Burst Size supported by DMA controller is increased to support bigger 5.74 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 5.75 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 5.76 -// For this Burst Size field of the control register is increased to 2 bits. 5.77 -// 3. Glitch is removed on the S_ACK_O signal. 5.78 -// 5.79 -// Version 7.0 5.80 -// 1. Initial Release 5.81 -// 5.82 +// : 5.83 +// Version : 7.0 5.84 +// : Initial Release 5.85 +// : 5.86 +// Version : 7.0SP2, 3.0 5.87 +// : 1. Read and Write channel of DMA controller are working in 5.88 +// : parallel, due to that now as soon as FIFO is not empty 5.89 +// : write channel of the DMA controller start writing data 5.90 +// : to the slave. 5.91 +// : 2. Burst Size supported by DMA controller is increased to 5.92 +// : support bigger burst (from current value of 4 and 8 to 5.93 +// : 16 and 32). Now 4 different type of burst sizes are 5.94 +// : supported by the DMA controller 4, 8, 16 and 32. For 5.95 +// : this Burst Size field of the control register is 5.96 +// : increased to 2 bits. 5.97 +// : 3. Glitch is removed on the S_ACK_O signal. 5.98 +// : 5.99 +// Version : 3.1 5.100 +// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 5.101 +// : which defines alignement of bytes in sub-word transfers. 5.102 +// : 5.103 +// Version : 3.2 5.104 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 5.105 +// : Read/Write Ports can be independently configured. 5.106 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 5.107 +// : retry results in the current burst or classic cycle 5.108 +// : being issued again after a retry timeout. 5.109 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 5.110 +// : results in the current dma transfer being terminated 5.111 +// : and the error is updated within the STATUS CSR. 5.112 +// : 4. Support for burst size of 64. 5.113 +// : 5.114 +// Version : 3.3 5.115 +// : Support for MachXO2 added. The MachXO2 only has a FIFO 5.116 +// : with separate read/write clocks. 5.117 // ============================================================================= 5.118 5.119 `ifndef MASTER_CTRL_FILE 5.120 `define MASTER_CTRL_FILE 5.121 `include "system_conf.v" 5.122 module MASTER_CTRL 5.123 - #(parameter LENGTH_WIDTH = 16, 5.124 + #(parameter MA_WB_DAT_WIDTH = 32, 5.125 + parameter MA_WB_ADR_WIDTH = 32, 5.126 + parameter MB_WB_DAT_WIDTH = 32, 5.127 + parameter MB_WB_ADR_WIDTH = 32, 5.128 + parameter S_WB_DAT_WIDTH = 32, 5.129 parameter FIFO_IMPLEMENTATION = "EBR") 5.130 - ( 5.131 - //master read port 5.132 - MA_ADR_O, 5.133 - MA_SEL_O, 5.134 - MA_WE_O, 5.135 - MA_STB_O, 5.136 - MA_CYC_O, 5.137 - MA_CTI_O, 5.138 - MA_LOCK_O, 5.139 - MA_DAT_I, //32bits 5.140 - MA_ACK_I, 5.141 - MA_ERR_I, 5.142 - MA_RTY_I, 5.143 - //master write port 5.144 - MB_ADR_O, 5.145 - MB_SEL_O, 5.146 - MB_DAT_O, //32bits 5.147 - MB_WE_O, 5.148 - MB_STB_O, 5.149 - MB_CYC_O, 5.150 - MB_CTI_O, 5.151 - MB_LOCK_O, 5.152 - MB_ACK_I, 5.153 - MB_ERR_I, 5.154 - MB_RTY_I, 5.155 - //register interface 5.156 - M_SEL_O, 5.157 - reg_start, 5.158 - reg_status, 5.159 - reg_interrupt, 5.160 - reg_busy, 5.161 - data_length, 5.162 - reg_cntlg, 5.163 - reg_bt2,reg_bt1,reg_bt0, 5.164 - incr_unit, 5.165 - reg_s_con, 5.166 - reg_d_con, 5.167 - reg_00_data, 5.168 - reg_04_data, 5.169 - //system clock and reset 5.170 - CLK_I, 5.171 - RST_I 5.172 - ); 5.173 - //master read port 5.174 - output [31:0] MA_ADR_O; 5.175 - output [3:0] MA_SEL_O; 5.176 - output MA_WE_O; 5.177 - output MA_STB_O; 5.178 - output MA_CYC_O; 5.179 - output [2:0] MA_CTI_O; 5.180 - output MA_LOCK_O; 5.181 - input [31:0] MA_DAT_I; //32bits 5.182 - input MA_ACK_I; 5.183 - input MA_ERR_I; 5.184 - input MA_RTY_I; 5.185 - //master write port 5.186 - output [31:0] MB_ADR_O; 5.187 - output [3:0] MB_SEL_O; 5.188 - output [31:0] MB_DAT_O; //32bits 5.189 - output MB_WE_O; 5.190 - output MB_STB_O; 5.191 - output MB_CYC_O; 5.192 - output [2:0] MB_CTI_O; 5.193 - output MB_LOCK_O; 5.194 - input MB_ACK_I; 5.195 - input MB_ERR_I; 5.196 - input MB_RTY_I; 5.197 - 5.198 - //register interface 5.199 - input [3:0] M_SEL_O; 5.200 - input reg_start; 5.201 - output reg_status; 5.202 - output reg_interrupt; 5.203 - output reg_busy; 5.204 - input [LENGTH_WIDTH-1:0] data_length; 5.205 - output reg_cntlg; 5.206 - input reg_bt2,reg_bt1,reg_bt0; 5.207 - input [2:0] incr_unit; 5.208 - input reg_s_con; 5.209 - input reg_d_con; 5.210 - input [31:0] reg_00_data; 5.211 - input [31:0] reg_04_data; 5.212 - //system clock and reset 5.213 - input CLK_I; 5.214 - input RST_I; 5.215 + ( 5.216 + // System clock and reset 5.217 + input CLK_I, 5.218 + input RST_I, 5.219 + // Master read port 5.220 + output reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 5.221 + output reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 5.222 + output reg [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 5.223 + output reg MA_WE_O, 5.224 + output reg MA_STB_O, 5.225 + output reg MA_CYC_O, 5.226 + output reg [2:0] MA_CTI_O, 5.227 + output reg MA_LOCK_O, 5.228 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 5.229 + input MA_ACK_I, 5.230 + input MA_ERR_I, 5.231 + input MA_RTY_I, 5.232 + // Master write port 5.233 + output reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 5.234 + output reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 5.235 + output reg [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 5.236 + output reg MB_WE_O, 5.237 + output reg MB_STB_O, 5.238 + output reg MB_CYC_O, 5.239 + output reg [2:0] MB_CTI_O, 5.240 + output reg MB_LOCK_O, 5.241 + input MB_ACK_I, 5.242 + input MB_ERR_I, 5.243 + input MB_RTY_I, 5.244 + // Register interface 5.245 + input reg_start, 5.246 + output reg reg_busy, 5.247 + output reg reg_status, 5.248 + output reg reg_interrupt, 5.249 + input reg_bt3, reg_bt2, reg_bt1, reg_bt0, 5.250 + input reg_s_con, reg_d_con, 5.251 + input reg_incw, reg_inchw, 5.252 + input [7:0] reg_rdelay, 5.253 + input [31:0] reg_00_data, 5.254 + input [31:0] reg_04_data, 5.255 + input [31:0] reg_08_data 5.256 + ); 5.257 + 5.258 + parameter lat_family = `LATTICE_FAMILY; 5.259 + parameter UDLY = 1; 5.260 + 5.261 + wire [MB_WB_DAT_WIDTH-1:0] fifo_dout; 5.262 + wire fifo_empty, fifo_aempty; 5.263 + reg [MA_WB_DAT_WIDTH-1:0] fifo_din; 5.264 + 5.265 + reg [31:0] xfer_length, xfer_length_nxt; 5.266 + reg [5:0] rburst_count, rburst_count_nxt; 5.267 + reg [5:0] wburst_count, wburst_count_nxt; 5.268 + reg [5:0] save_wburst_count, save_wburst_count_nxt; 5.269 + reg [31:0] raddr_checkpoint, raddr_checkpoint_nxt, waddr_checkpoint, waddr_checkpoint_nxt; 5.270 + reg [7:0] retry_delay, retry_delay_nxt; 5.271 + reg MA_CYC_O_nxt, MA_STB_O_nxt, MA_CYC_O_d; 5.272 + reg [2:0] MA_CTI_O_nxt; 5.273 + reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O_nxt; 5.274 + reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O_nxt; 5.275 + reg MB_CYC_O_nxt, MB_STB_O_nxt, MB_CYC_O_d; 5.276 + reg [2:0] MB_CTI_O_nxt; 5.277 + reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O_nxt; 5.278 + reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O_nxt; 5.279 + reg reg_status_nxt; 5.280 + reg burst_start, xfer_done; 5.281 + wire [2:0] iCount; 5.282 + wire [5:0] bCount; 5.283 + wire [8:0] biCount; 5.284 + 5.285 + /*---------------------------------------------------------------------- 5.286 + 5.287 + READ State Machine 5.288 + 5.289 + ----------------------------------------------------------------------*/ 5.290 + reg [2:0] rstate, rstate_nxt; 5.291 + parameter RD_IDLE = 3'b000; 5.292 + parameter RD_SINGLEA = 3'b001; 5.293 + parameter RD_SINGLEB = 3'b010; 5.294 + parameter RD_SINGLE_RETRY = 3'b011; 5.295 + parameter RD_BURST = 3'b100; 5.296 + 5.297 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ERR_I or MA_RTY_I or MB_ERR_I 5.298 + or MB_RTY_I or burst_start or rburst_count or reg_bt3 5.299 + or reg_start or retry_delay or rstate or xfer_done) 5.300 + casez (rstate) 5.301 + RD_IDLE: 5.302 + if (reg_start && (reg_bt3 == 1'b0)) 5.303 + rstate_nxt = RD_SINGLEA; 5.304 + else if (burst_start && reg_bt3) 5.305 + rstate_nxt = RD_BURST; 5.306 + else 5.307 + rstate_nxt = rstate; 5.308 + 5.309 + RD_SINGLEA: 5.310 + if (MA_ACK_I) 5.311 + rstate_nxt = RD_SINGLEB; 5.312 + else if (MA_ERR_I) 5.313 + rstate_nxt = RD_IDLE; 5.314 + else if (MA_RTY_I) 5.315 + rstate_nxt = RD_SINGLE_RETRY; 5.316 + else 5.317 + rstate_nxt = rstate; 5.318 + 5.319 + RD_SINGLEB: 5.320 + if (burst_start) 5.321 + rstate_nxt = RD_SINGLEA; 5.322 + else if (MB_ERR_I || xfer_done) 5.323 + rstate_nxt = RD_IDLE; 5.324 + else if (MB_RTY_I) 5.325 + rstate_nxt = RD_SINGLE_RETRY; 5.326 + else 5.327 + rstate_nxt = rstate; 5.328 + 5.329 + RD_BURST: 5.330 + if (MB_ERR_I || MB_RTY_I || MA_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 0))) 5.331 + rstate_nxt = RD_IDLE; 5.332 + else 5.333 + rstate_nxt = rstate; 5.334 + 5.335 + RD_SINGLE_RETRY: 5.336 + if (retry_delay == 8'h0) 5.337 + rstate_nxt = RD_SINGLEA; 5.338 + else 5.339 + rstate_nxt = rstate; 5.340 + 5.341 + default: 5.342 + rstate_nxt = RD_IDLE; 5.343 + endcase 5.344 + 5.345 + /*---------------------------------------------------------------------- 5.346 + 5.347 + WRITE State Machine 5.348 + 5.349 + ----------------------------------------------------------------------*/ 5.350 + reg [3:0] wstate, wstate_nxt; 5.351 + parameter WR_IDLE = 4'b0000; 5.352 + parameter WR_SINGLEA = 4'b0001; 5.353 + parameter WR_SINGLEB = 4'b0010; 5.354 + parameter WR_FIFO_CHECK = 4'b0011; 5.355 + parameter WR_SHORT = 4'b0100; 5.356 + parameter WR_BURST = 4'b0101; 5.357 + parameter WR_SBURST = 4'b0110; 5.358 + parameter WR_SETUPA = 4'b0111; 5.359 + parameter WR_SETUPB = 4'b1000; 5.360 + parameter WR_ERROR = 4'b1001; 5.361 + parameter WR_RETRY = 4'b1010; 5.362 + 5.363 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ERR_I 5.364 + or MB_RTY_I or fifo_aempty or fifo_empty or iCount 5.365 + or reg_bt3 or reg_start or retry_delay or wburst_count 5.366 + or wstate or xfer_length) 5.367 + casez (wstate) 5.368 + WR_IDLE: 5.369 + if (reg_start) 5.370 + wstate_nxt = reg_bt3 ? WR_SETUPA : WR_SINGLEA; 5.371 + else 5.372 + wstate_nxt = wstate; 5.373 + 5.374 + WR_SINGLEA: 5.375 + if (MA_ERR_I) 5.376 + wstate_nxt = WR_IDLE; 5.377 + else if (fifo_empty == 1'b0) 5.378 + wstate_nxt = WR_SINGLEB; 5.379 + else 5.380 + wstate_nxt = wstate; 5.381 + 5.382 + WR_SINGLEB: 5.383 + if (MB_ACK_I) 5.384 + wstate_nxt = (xfer_length == iCount) ? WR_IDLE : WR_SINGLEA; 5.385 + else if (MB_ERR_I) 5.386 + wstate_nxt = WR_IDLE; 5.387 + else if (MB_RTY_I) 5.388 + wstate_nxt = WR_SINGLEA; 5.389 + else 5.390 + wstate_nxt = wstate; 5.391 + 5.392 + WR_FIFO_CHECK: 5.393 + if (MA_ERR_I) 5.394 + wstate_nxt = WR_ERROR; 5.395 + else if (MA_RTY_I) 5.396 + wstate_nxt = WR_RETRY; 5.397 + else 5.398 + if ((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.399 + wstate_nxt = WR_SHORT; 5.400 + else if ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)) 5.401 + wstate_nxt = WR_BURST; 5.402 + else 5.403 + wstate_nxt = wstate; 5.404 + 5.405 + WR_SHORT: 5.406 + if (MA_ERR_I) 5.407 + wstate_nxt = WR_ERROR; 5.408 + else if (MA_RTY_I) 5.409 + wstate_nxt = WR_RETRY; 5.410 + else 5.411 + if (MB_ACK_I) 5.412 + wstate_nxt = WR_FIFO_CHECK; 5.413 + else if (MB_ERR_I) 5.414 + wstate_nxt = WR_ERROR; 5.415 + else if (MB_RTY_I) 5.416 + wstate_nxt = WR_RETRY; 5.417 + else 5.418 + wstate_nxt = wstate; 5.419 + 5.420 + WR_BURST: 5.421 + if (MA_ERR_I) 5.422 + wstate_nxt = WR_ERROR; 5.423 + else if (MA_RTY_I) 5.424 + wstate_nxt = WR_RETRY; 5.425 + else 5.426 + if (MB_ACK_I) 5.427 + if (fifo_aempty && (wburst_count >= 6'h2)) 5.428 + wstate_nxt = WR_SBURST; 5.429 + else if (wburst_count == 6'h0) 5.430 + wstate_nxt = WR_SETUPA; 5.431 + else 5.432 + wstate_nxt = wstate; 5.433 + else if (MB_ERR_I) 5.434 + wstate_nxt = WR_ERROR; 5.435 + else if (MB_RTY_I) 5.436 + wstate_nxt = WR_RETRY; 5.437 + else 5.438 + wstate_nxt = wstate; 5.439 + 5.440 + WR_SBURST: 5.441 + if (MA_ERR_I) 5.442 + wstate_nxt = WR_ERROR; 5.443 + else if (MA_RTY_I) 5.444 + wstate_nxt = WR_RETRY; 5.445 + else 5.446 + if (MB_ACK_I) 5.447 + wstate_nxt = WR_FIFO_CHECK; 5.448 + else if (MB_RTY_I) 5.449 + wstate_nxt = WR_RETRY; 5.450 + else 5.451 + wstate_nxt = wstate; 5.452 + 5.453 + WR_SETUPA: 5.454 + wstate_nxt = WR_SETUPB; 5.455 + 5.456 + WR_SETUPB: 5.457 + wstate_nxt = (wburst_count == 6'h0) ? WR_IDLE : WR_FIFO_CHECK; 5.458 + 5.459 + WR_ERROR: 5.460 + wstate_nxt = fifo_empty ? WR_IDLE : wstate; 5.461 + 5.462 + WR_RETRY: 5.463 + if (fifo_empty && (retry_delay == 8'h0)) 5.464 + wstate_nxt = WR_FIFO_CHECK; 5.465 + else 5.466 + wstate_nxt = wstate; 5.467 + 5.468 + default: 5.469 + wstate_nxt = WR_IDLE; 5.470 + endcase 5.471 + 5.472 + /*---------------------------------------------------------------------- 5.473 + Status Signals 5.474 + ----------------------------------------------------------------------*/ 5.475 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ERR_I or reg_status or wstate 5.476 + or wstate_nxt) 5.477 + begin 5.478 + // Raise and hold busy signal until current DMA transfer is complete 5.479 + reg_busy = (wstate_nxt != WR_IDLE); 5.480 + 5.481 + // Raise and hold error signal until a new DMA transfer is initiated. 5.482 + // Error signal is raised when the WISHBONE cycle results in _ERR_I 5.483 + if ((wstate == WR_IDLE) && (wstate_nxt != WR_IDLE)) 5.484 + reg_status_nxt = 1'b0; 5.485 + else if (MA_ERR_I || MB_ERR_I) 5.486 + reg_status_nxt = 1'b1; 5.487 + else 5.488 + reg_status_nxt = reg_status; 5.489 + 5.490 + // Raise interrupt on completion of DMA transfer 5.491 + reg_interrupt = (wstate != WR_IDLE) & (wstate_nxt == WR_IDLE); 5.492 + end 5.493 + 5.494 + /*---------------------------------------------------------------------- 5.495 + WISHBONE Read Port 5.496 + ----------------------------------------------------------------------*/ 5.497 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ADR_O or MA_CTI_O or MA_CYC_O 5.498 + or MA_CYC_O_d or MA_ERR_I or MA_RTY_I or MA_STB_O 5.499 + or MB_ERR_I or MB_RTY_I or burst_start or iCount 5.500 + or raddr_checkpoint or rburst_count or reg_00_data 5.501 + or reg_bt3 or reg_s_con or reg_start or rstate 5.502 + or rstate_nxt) 5.503 + begin 5.504 + // MA_CYC_O and MA_STB_O 5.505 + 5.506 + // handle all conditions that cause MA_CYC_O to go 0 5.507 + if (((rstate == RD_SINGLEA) 5.508 + && (MA_ACK_I || MA_ERR_I || MA_RTY_I)) 5.509 + || ((rstate == RD_BURST) 5.510 + && (MB_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 6'h0))))) 5.511 + begin 5.512 + MA_CYC_O_nxt = 1'b0; 5.513 + MA_STB_O_nxt = 1'b0; 5.514 + end 5.515 + // handle all conditions that cause MA_CYC_O to go 1 5.516 + else if (((rstate_nxt == RD_SINGLEA) 5.517 + && ((rstate == RD_IDLE) || (rstate == RD_SINGLEB) || (rstate == RD_SINGLE_RETRY))) 5.518 + || ((rstate == RD_BURST) && (MA_CYC_O_d == 1'b0))) 5.519 + begin 5.520 + MA_CYC_O_nxt = 1'b1; 5.521 + MA_STB_O_nxt = 1'b1; 5.522 + end 5.523 + // default: maintain state 5.524 + else 5.525 + begin 5.526 + MA_CYC_O_nxt = MA_CYC_O; 5.527 + MA_STB_O_nxt = MA_STB_O; 5.528 + end 5.529 + 5.530 + 5.531 + // MA_ADR_O 5.532 + 5.533 + // set up first address of the dma transfer 5.534 + if (reg_start) 5.535 + MA_ADR_O_nxt = reg_00_data; 5.536 + else if (reg_s_con == 1'b0) 5.537 + begin 5.538 + // roll back to first address in a burst transfer on a retry 5.539 + if (/*(rstate == RD_BURST) && */MB_RTY_I) 5.540 + MA_ADR_O_nxt = raddr_checkpoint; 5.541 + // increment for every regular transfer 5.542 + else if ((MB_RTY_I == 1'b0) 5.543 + && (((rstate == RD_SINGLEB) && burst_start) 5.544 + || ((rstate == RD_BURST) && MA_ACK_I))) 5.545 + MA_ADR_O_nxt = MA_ADR_O + iCount; 5.546 + else 5.547 + MA_ADR_O_nxt = MA_ADR_O; 5.548 + end 5.549 + else 5.550 + MA_ADR_O_nxt = MA_ADR_O; 5.551 + 5.552 + 5.553 + // MA_CTI_O 5.554 + 5.555 + if (reg_start || burst_start) 5.556 + MA_CTI_O_nxt = reg_bt3 ? (reg_s_con ? 3'b001 : 3'b010) : 3'b000; 5.557 + else if ((rstate == RD_BURST) && (rburst_count == 6'h1) && MA_ACK_I) 5.558 + MA_CTI_O_nxt = 3'b111; 5.559 + else 5.560 + MA_CTI_O_nxt = MA_CTI_O; 5.561 + 5.562 + 5.563 + // Other signals 5.564 + MA_WE_O = 1'b0; 5.565 + MA_DAT_O = 0; 5.566 + MA_LOCK_O = 1'b0; 5.567 + end 5.568 + 5.569 + generate 5.570 + if (MA_WB_DAT_WIDTH == 8) begin 5.571 + 5.572 + always @(*) 5.573 + MA_SEL_O_nxt = 1'b1; 5.574 + 5.575 + end 5.576 + else begin 5.577 + 5.578 + always @(/*AUTOSENSE*/MA_ADR_O_nxt or iCount) 5.579 + begin 5.580 + if (iCount == 1) 5.581 + casez (MA_ADR_O_nxt[1:0]) 5.582 + 2'b00: MA_SEL_O_nxt = 4'b1000; 5.583 + 2'b01: MA_SEL_O_nxt = 4'b0100; 5.584 + 2'b10: MA_SEL_O_nxt = 4'b0010; 5.585 + 2'b11: MA_SEL_O_nxt = 4'b0001; 5.586 + default: 5.587 + MA_SEL_O_nxt = 4'b1111; 5.588 + endcase 5.589 + else if (iCount == 2) 5.590 + MA_SEL_O_nxt = MA_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 5.591 + else 5.592 + MA_SEL_O_nxt = 4'b1111; 5.593 + end 5.594 + 5.595 + end 5.596 + endgenerate 5.597 + 5.598 + 5.599 + /*---------------------------------------------------------------------- 5.600 + WISHBONE Write Port 5.601 + ----------------------------------------------------------------------*/ 5.602 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ADR_O 5.603 + or MB_CTI_O or MB_CYC_O or MB_ERR_I or MB_RTY_I 5.604 + or MB_STB_O or fifo_aempty or fifo_dout or fifo_empty 5.605 + or iCount or reg_04_data or reg_d_con or reg_s_con 5.606 + or reg_start or waddr_checkpoint or wburst_count or wstate 5.607 + or wstate_nxt) 5.608 + begin 5.609 + // MB_CYC_O and MB_STB_O 5.610 + 5.611 + // handle all conditions that cause MB_CYC_O to go 0 5.612 + if (((wstate == WR_SINGLEB) 5.613 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I)) 5.614 + || ((MA_ERR_I || MA_RTY_I) 5.615 + && ((wstate == WR_SHORT) || (wstate == WR_FIFO_CHECK) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 5.616 + || ((wstate == WR_BURST) 5.617 + && ((MB_ACK_I && (wburst_count == 6'h0)) || MB_ERR_I || MB_RTY_I)) 5.618 + || ((wstate == WR_SBURST) 5.619 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I))) 5.620 + begin 5.621 + MB_CYC_O_nxt = 1'b0; 5.622 + MB_STB_O_nxt = 1'b0; 5.623 + end 5.624 + // handle all conditions that cause MB_CYC_O to go 1 5.625 + else if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 5.626 + || ((wstate == WR_FIFO_CHECK) 5.627 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.628 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))))) 5.629 + begin 5.630 + MB_CYC_O_nxt = 1'b1; 5.631 + MB_STB_O_nxt = 1'b1; 5.632 + end 5.633 + // default: maintain state 5.634 + else 5.635 + begin 5.636 + MB_CYC_O_nxt = MB_CYC_O; 5.637 + MB_STB_O_nxt = MB_STB_O; 5.638 + end 5.639 + 5.640 + 5.641 + // MB_ADR_O 5.642 + 5.643 + // set up first address of the dma transfer 5.644 + if (reg_start) 5.645 + MB_ADR_O_nxt = reg_04_data; 5.646 + else if (reg_d_con == 1'b0) 5.647 + begin 5.648 + // roll back to first address in a burst transfer on a retry 5.649 + if (wstate == WR_RETRY) 5.650 + MB_ADR_O_nxt = waddr_checkpoint; 5.651 + // increment for every regular transfer 5.652 + else if (((wstate == WR_SINGLEB) && MB_ACK_I) 5.653 + || (MB_ACK_I && (MA_RTY_I == 1'b0) && (MA_ERR_I == 1'b0) 5.654 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST)))) 5.655 + MB_ADR_O_nxt = MB_ADR_O + iCount; 5.656 + else 5.657 + MB_ADR_O_nxt = MB_ADR_O; 5.658 + end 5.659 + else 5.660 + MB_ADR_O_nxt = MB_ADR_O; 5.661 + 5.662 + 5.663 + // MB_CTI_O 5.664 + 5.665 + // set up classic wishbone cycle 5.666 + if ((wstate == WR_SINGLEA) 5.667 + || ((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_SHORT))) 5.668 + MB_CTI_O_nxt = 3'b000; 5.669 + // set up termination of a wishbone burst cycle 5.670 + else if ((wstate == WR_BURST) 5.671 + && ((MB_ACK_I && (wburst_count == 6'h1)) || (wstate_nxt == WR_SBURST))) 5.672 + MB_CTI_O_nxt = 3'b111; 5.673 + // set up wishbone burst (incrementing or constant address) 5.674 + else if (((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_BURST)) 5.675 + || ((wstate == WR_BURST) && MB_ACK_I)) 5.676 + MB_CTI_O_nxt = reg_s_con ? 3'b001 : 3'b010; 5.677 + // hold 5.678 + else 5.679 + MB_CTI_O_nxt = MB_CTI_O; 5.680 + 5.681 + // MB_DAT_O 5.682 + MB_DAT_O = fifo_dout; 5.683 + 5.684 + 5.685 + // Other signals 5.686 + MB_WE_O = 1'b1; 5.687 + MB_LOCK_O = 1'b0; 5.688 + end 5.689 + 5.690 + generate 5.691 + if (MB_WB_DAT_WIDTH == 8) begin 5.692 + 5.693 + always @(*) 5.694 + MB_SEL_O_nxt = 1'b1; 5.695 + 5.696 + end 5.697 + else begin 5.698 + 5.699 + always @(/*AUTOSENSE*/MB_ADR_O_nxt or iCount) 5.700 + begin 5.701 + if (iCount == 1) 5.702 + casez (MB_ADR_O_nxt[1:0]) 5.703 + 2'b00: MB_SEL_O_nxt = 4'b1000; 5.704 + 2'b01: MB_SEL_O_nxt = 4'b0100; 5.705 + 2'b10: MB_SEL_O_nxt = 4'b0010; 5.706 + 2'b11: MB_SEL_O_nxt = 4'b0001; 5.707 + default: 5.708 + MB_SEL_O_nxt = 4'b1111; 5.709 + endcase 5.710 + else if (iCount == 2) 5.711 + MB_SEL_O_nxt = MB_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 5.712 + else 5.713 + MB_SEL_O_nxt = 4'b1111; 5.714 + end 5.715 + 5.716 + end 5.717 + endgenerate 5.718 + 5.719 + /*---------------------------------------------------------------------- 5.720 + Logic to keep track of where we are in the transfer process 5.721 + ----------------------------------------------------------------------*/ 5.722 + // Increment Count 5.723 + generate 5.724 + if (S_WB_DAT_WIDTH == 8) begin 5.725 + assign iCount = 3'h1; 5.726 + end 5.727 + else begin 5.728 + assign iCount = reg_incw ? 3'h4 : (reg_inchw ? 3'h2 : 3'h1); 5.729 + end 5.730 + endgenerate 5.731 + 5.732 + // Burst Count 5.733 + assign bCount = (reg_bt3 5.734 + ? (reg_bt2 5.735 + ? 6'h3f 5.736 + : (reg_bt1 5.737 + ? (reg_bt0 ? 6'h1f : 6'h0f) 5.738 + : (reg_bt0 ? 6'h07 : 6'h03))) 5.739 + : 6'h01 5.740 + ); 5.741 + 5.742 + // Burst Increment Count 5.743 + assign biCount = (reg_bt3 5.744 + ? (reg_bt2 5.745 + ? iCount<<6 5.746 + : (reg_bt1 5.747 + ? (reg_bt0 ? iCount<<5 : iCount<<4) 5.748 + : (reg_bt0 ? iCount<<3 : iCount<<2) 5.749 + ) 5.750 + ) 5.751 + : iCount 5.752 + ); 5.753 + 5.754 + always @(/*AUTOSENSE*/MA_ACK_I or MB_ACK_I or bCount or biCount 5.755 + or fifo_empty or iCount or rburst_count or reg_08_data 5.756 + or reg_inchw or reg_incw or reg_start or rstate 5.757 + or save_wburst_count or wburst_count or wstate 5.758 + or xfer_length) 5.759 + begin 5.760 + // Transfer Length 5.761 + if (reg_start && (wstate == WR_IDLE)) 5.762 + xfer_length_nxt = reg_08_data; 5.763 + else if (MB_ACK_I && (wstate == WR_SINGLEB)) 5.764 + xfer_length_nxt = xfer_length - iCount; 5.765 + else if (wstate == WR_SETUPA) 5.766 + xfer_length_nxt = (xfer_length >= biCount) ? (xfer_length - biCount) : 0; 5.767 + else 5.768 + xfer_length_nxt = xfer_length; 5.769 + 5.770 + // Read-side Burst Count 5.771 + if (rstate == RD_IDLE) 5.772 + rburst_count_nxt = wburst_count; 5.773 + else if ((rstate == RD_BURST) && MA_ACK_I) 5.774 + rburst_count_nxt = rburst_count - 1'b1; 5.775 + else 5.776 + rburst_count_nxt = rburst_count; 5.777 + 5.778 + // Write-side Burst Count 5.779 + if (wstate == WR_SETUPA) 5.780 + wburst_count_nxt = ((xfer_length == 0) 5.781 + ? 0 5.782 + : ((xfer_length >= biCount) 5.783 + ? bCount 5.784 + : (xfer_length-1)>>(reg_incw ? 2 : (reg_inchw ? 1 : 0)))); 5.785 + else if ((wstate == WR_RETRY) && fifo_empty) 5.786 + wburst_count_nxt = save_wburst_count; 5.787 + else if (MB_ACK_I 5.788 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 5.789 + wburst_count_nxt = wburst_count - 1'b1; 5.790 + else 5.791 + wburst_count_nxt = wburst_count; 5.792 + end 5.793 + 5.794 + /*---------------------------------------------------------------------- 5.795 + Logic to support a burst retry 5.796 + ----------------------------------------------------------------------*/ 5.797 + always @(/*AUTOSENSE*/MA_ADR_O or MB_ADR_O or raddr_checkpoint 5.798 + or reg_rdelay or retry_delay or rstate or rstate_nxt 5.799 + or save_wburst_count or waddr_checkpoint 5.800 + or wburst_count_nxt or wstate or wstate_nxt) 5.801 + begin 5.802 + // Write-side Saved Burst Count 5.803 + if (wstate == WR_SETUPA) 5.804 + save_wburst_count_nxt = wburst_count_nxt; 5.805 + else 5.806 + save_wburst_count_nxt = save_wburst_count; 5.807 + 5.808 + // Retry Delay 5.809 + if (((wstate != WR_RETRY) && (wstate_nxt == WR_RETRY)) 5.810 + || ((rstate == RD_SINGLEA) && (rstate_nxt == RD_SINGLE_RETRY))) 5.811 + retry_delay_nxt = reg_rdelay; 5.812 + else if ((wstate == WR_RETRY) || (rstate == RD_SINGLE_RETRY)) 5.813 + retry_delay_nxt = retry_delay - 1'b1; 5.814 + else 5.815 + retry_delay_nxt = retry_delay; 5.816 + 5.817 + // Read Address Checkpoint 5.818 + if ((rstate == RD_IDLE) && (rstate_nxt == RD_BURST)) 5.819 + raddr_checkpoint_nxt = MA_ADR_O; 5.820 + else 5.821 + raddr_checkpoint_nxt = raddr_checkpoint; 5.822 + 5.823 + // Write Address Checkpoint 5.824 + if (wstate == WR_SETUPA) 5.825 + waddr_checkpoint_nxt = MB_ADR_O; 5.826 + else 5.827 + waddr_checkpoint_nxt = waddr_checkpoint; 5.828 + end 5.829 + 5.830 + /*---------------------------------------------------------------------- 5.831 + Logic to indicate start/end of transfer and bursts 5.832 + ----------------------------------------------------------------------*/ 5.833 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ACK_I or MB_ERR_I or iCount 5.834 + or retry_delay or wburst_count or wstate or xfer_length) 5.835 + begin 5.836 + if (((wstate == WR_SINGLEB) && (xfer_length > iCount) && MB_ACK_I) 5.837 + || ((wstate == WR_SETUPB) && (wburst_count > 0)) 5.838 + || ((wstate == WR_RETRY) && (retry_delay == 8'b0))) 5.839 + burst_start = 1'b1; 5.840 + else 5.841 + burst_start = 1'b0; 5.842 + 5.843 + if (MB_ERR_I 5.844 + || MA_ERR_I 5.845 + || ((wstate == WR_SINGLEB) && (xfer_length == iCount) && MB_ACK_I) 5.846 + || ((wstate == WR_SETUPB) && (wburst_count == 0))) 5.847 + xfer_done = 1'b1; 5.848 + else 5.849 + xfer_done = 1'b0; 5.850 + end 5.851 5.852 - parameter lat_family = `LATTICE_FAMILY; 5.853 - parameter UDLY = 1; 5.854 - //Read FSM States encoding 5.855 - parameter ST_IDLE = 3'b000; 5.856 - parameter ST_READ = 3'b001; 5.857 - parameter ST_RDADDR = 3'b010; 5.858 - parameter ST_RDFIFO = 3'b011; 5.859 - parameter ST_WAIT_WRITE_FINISH = 3'b100; 5.860 - 5.861 - //Write FSM States encoding 5.862 - parameter ST_WRITE_IDLE = 4'b0000; 5.863 - parameter ST_WRITE = 4'b0001; 5.864 - parameter ST_WRADDR = 4'b0010; 5.865 - parameter ST_CNTLNGTH = 4'b0011; 5.866 - parameter ST_JUSTICE = 4'b0100; 5.867 - parameter ST_FIFO_EMPTY = 4'b0101; 5.868 - parameter ST_WRITE_WAIT = 4'b0110; 5.869 - parameter ST_FIFO_AEMPTY = 4'b1010; 5.870 - parameter ST_FIFO_RESUME = 4'b1000; 5.871 - 5.872 - // FSM for normal data transfer 5.873 - parameter ST_IDLE1 = 3'b000; 5.874 - parameter ST_READ1 = 3'b001; 5.875 - parameter ST_WRITE1 = 3'b010; 5.876 - parameter ST_RDADDR1 = 3'b011; 5.877 - parameter ST_WRADDR1 = 3'b100; 5.878 - parameter ST_CNTLNGTH1 = 3'b101; 5.879 - parameter ST_JUSTICE1 = 3'b110; 5.880 - parameter ST_RDFIFO1 = 3'b111; 5.881 - reg [2:0] status; 5.882 - reg var_length; 5.883 - 5.884 - 5.885 - //fifo status 5.886 - 5.887 - reg [2:0] status1; 5.888 - reg [3:0] status2; 5.889 - reg var_length2; 5.890 - reg var_length1; 5.891 - reg MA_STB_O; 5.892 - reg MB_STB_O; 5.893 - reg MA_CYC_O; 5.894 - reg MB_CYC_O; 5.895 - reg [2:0] MA_CTI_O; 5.896 - reg [2:0] MB_CTI_O; 5.897 - wire MA_WE_O = 1'b0; 5.898 - wire MB_WE_O = 1'b1; 5.899 - reg [31:0] MA_ADR_O; 5.900 - reg [31:0] MB_ADR_O; 5.901 - reg [3:0] MA_SEL_O; 5.902 - reg [3:0] MB_SEL_O; 5.903 - wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0; 5.904 - wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0; 5.905 - 5.906 - wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1); 5.907 - wire reg_interrupt; 5.908 - wire reg_status; 5.909 - 5.910 - wire reg_cntlg; 5.911 - reg start_flag; 5.912 - reg [5:0] burst_size; 5.913 - reg [5:0] burst_cnt; 5.914 - reg fifo_wr; 5.915 - reg fifo_rd; 5.916 - reg [31:0] fifo_din; 5.917 - wire [31:0] fifo_dout; 5.918 - wire fifo_empty; 5.919 - wire fifo_aempty; 5.920 - reg fifo_clear; 5.921 - reg [31:0] first_data; 5.922 - reg first_data_flag; 5.923 - wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout; 5.924 - reg latch_start; 5.925 - 5.926 - reg reg_status1, reg_status2; 5.927 - reg reg_interrupt1, reg_interrupt2; 5.928 - reg end_of_transfer; 5.929 - reg burst_completed; 5.930 - reg donot_start_again; 5.931 - reg [5:0] burst_size2; 5.932 - reg [5:0] burst_cnt2; 5.933 - 5.934 - reg reg_cntlg_burst, reg_cntlg_normal; 5.935 - reg reg_status_normal, reg_interrupt_normal; 5.936 - reg direct_data; 5.937 - 5.938 + /*---------------------------------------------------------------------- 5.939 + Sequential Logic 5.940 + ----------------------------------------------------------------------*/ 5.941 always @(posedge CLK_I or posedge RST_I) 5.942 - if(RST_I) 5.943 - begin 5.944 - first_data <= #UDLY 'h0; 5.945 - first_data_flag <= #UDLY 1'b0; 5.946 - end 5.947 - else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I) 5.948 + if (RST_I) 5.949 begin 5.950 - first_data <= #UDLY MA_DAT_I; 5.951 - first_data_flag <= #UDLY 1'b1; 5.952 + rstate <= #UDLY RD_IDLE; 5.953 + wstate <= #UDLY WR_IDLE; 5.954 + xfer_length <= #UDLY 32'b0; 5.955 + rburst_count <= #UDLY 6'b0; 5.956 + wburst_count <= #UDLY 6'b0; 5.957 + retry_delay <= #UDLY 8'b0; 5.958 + reg_status <= #UDLY 1'b0; 5.959 + MA_CYC_O <= #UDLY 1'b0; 5.960 + MA_CYC_O_d <= #UDLY 1'b0; 5.961 + MA_STB_O <= #UDLY 1'b0; 5.962 + MA_CTI_O <= #UDLY 3'b0; 5.963 + MA_ADR_O <= #UDLY 'b0; 5.964 + MA_SEL_O <= #UDLY 'b0; 5.965 + MB_CYC_O <= #UDLY 1'b0; 5.966 + MB_CYC_O_d <= #UDLY 1'b0; 5.967 + MB_STB_O <= #UDLY 1'b0; 5.968 + MB_CTI_O <= #UDLY 3'b0; 5.969 + MB_ADR_O <= #UDLY 'b0; 5.970 + MB_SEL_O <= #UDLY 'b0; 5.971 + raddr_checkpoint <= #UDLY 32'b0; 5.972 + waddr_checkpoint <= #UDLY 32'b0; 5.973 + save_wburst_count <= #UDLY 6'b0; 5.974 end 5.975 - else if(first_data_flag & MB_ACK_I) 5.976 + else 5.977 begin 5.978 - first_data_flag <= #UDLY 1'b0; 5.979 + rstate <= #UDLY rstate_nxt; 5.980 + wstate <= #UDLY wstate_nxt; 5.981 + xfer_length <= #UDLY xfer_length_nxt; 5.982 + rburst_count <= #UDLY rburst_count_nxt; 5.983 + wburst_count <= #UDLY wburst_count_nxt; 5.984 + retry_delay <= #UDLY retry_delay_nxt; 5.985 + reg_status <= #UDLY reg_status_nxt; 5.986 + MA_CYC_O <= #UDLY MA_CYC_O_nxt; 5.987 + MA_CYC_O_d <= #UDLY MA_CYC_O; 5.988 + MA_STB_O <= #UDLY MA_STB_O_nxt; 5.989 + MA_CTI_O <= #UDLY MA_CTI_O_nxt; 5.990 + MA_ADR_O <= #UDLY MA_ADR_O_nxt; 5.991 + MA_SEL_O <= #UDLY MA_SEL_O_nxt; 5.992 + MB_CYC_O <= #UDLY MB_CYC_O_nxt; 5.993 + MB_CYC_O_d <= #UDLY MB_CYC_O; 5.994 + MB_STB_O <= #UDLY MB_STB_O_nxt; 5.995 + MB_CTI_O <= #UDLY MB_CTI_O_nxt; 5.996 + MB_ADR_O <= #UDLY MB_ADR_O_nxt; 5.997 + MB_SEL_O <= #UDLY MB_SEL_O_nxt; 5.998 + raddr_checkpoint <= #UDLY raddr_checkpoint_nxt; 5.999 + waddr_checkpoint <= #UDLY waddr_checkpoint_nxt; 5.1000 + save_wburst_count <= #UDLY save_wburst_count_nxt; 5.1001 end 5.1002 5.1003 - assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal; 5.1004 - assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal; 5.1005 - assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal; 5.1006 - 5.1007 - 5.1008 - //FSM 5.1009 - always @(posedge CLK_I or posedge RST_I) 5.1010 - if(RST_I) 5.1011 - begin 5.1012 - status1 <= #UDLY ST_IDLE; 5.1013 - var_length1 <= #UDLY 1'b0; 5.1014 - MA_ADR_O <= #UDLY 32'h0; 5.1015 - MA_SEL_O <= #UDLY 4'b1111; 5.1016 - MA_CYC_O <= #UDLY 1'b0; 5.1017 - MA_CTI_O <= #UDLY 3'h0; 5.1018 - MA_STB_O <= #UDLY 1'b0; 5.1019 - reg_status1 <= #UDLY 1'b0; 5.1020 - reg_interrupt1 <= #UDLY 1'b0; 5.1021 - start_flag <= #UDLY 1'b0; 5.1022 - burst_size <= #UDLY 5'h0; 5.1023 - burst_cnt <= #UDLY 5'h0; 5.1024 - fifo_clear <= #UDLY 1'b0; 5.1025 - latch_start <= #UDLY 1'b0; 5.1026 - fifo_wr <= #UDLY 1'b0; 5.1027 - 5.1028 - status2 <= #UDLY ST_WRITE_IDLE; 5.1029 - MB_ADR_O <= #UDLY 32'h0; 5.1030 - MB_SEL_O <= #UDLY 4'b1111; 5.1031 - MB_CYC_O <= #UDLY 1'b0; 5.1032 - MB_CTI_O <= #UDLY 3'h0; 5.1033 - MB_STB_O <= #UDLY 1'b0; 5.1034 - reg_status2 <= #UDLY 1'b0; 5.1035 - reg_interrupt2 <= #UDLY 1'b0; 5.1036 - reg_cntlg_burst <= #UDLY 1'b0; 5.1037 - burst_size2 <= #UDLY 5'h0; 5.1038 - burst_cnt2 <= #UDLY 5'h0; 5.1039 - fifo_rd <= #UDLY 1'b0; 5.1040 - end_of_transfer <= #UDLY 1'b0; 5.1041 - var_length2 <= #UDLY 1'b0; 5.1042 - burst_completed <= #UDLY 1'b0; 5.1043 - donot_start_again <= #UDLY 1'b0; 5.1044 - 5.1045 - status <= #UDLY ST_IDLE1; 5.1046 - var_length <= #UDLY 1'b0; 5.1047 - reg_status_normal <= #UDLY 1'b0; 5.1048 - reg_interrupt_normal <= #UDLY 1'b0; 5.1049 - reg_cntlg_normal <= #UDLY 1'b0; 5.1050 - direct_data <= #UDLY 1'b0; 5.1051 - end 5.1052 - else 5.1053 - begin 5.1054 - if (reg_bt2) begin 5.1055 - // Read Burst 5.1056 - if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE))) 5.1057 - begin 5.1058 - status1 <= #UDLY ST_IDLE; 5.1059 - end 5.1060 - else 5.1061 - begin 5.1062 - case(status1) 5.1063 - ST_IDLE: 5.1064 - begin 5.1065 - if(fifo_wr) 5.1066 - fifo_wr <= #UDLY 1'b0; 5.1067 - if(MA_ACK_I) 5.1068 - begin 5.1069 - MA_CYC_O <= #UDLY 1'b0; 5.1070 - MA_STB_O <= #UDLY 1'b0; 5.1071 - MA_CTI_O <= #UDLY 3'h0; 5.1072 - end 5.1073 - if(reg_start | latch_start) 5.1074 - begin 5.1075 - if(fifo_empty) 5.1076 - begin 5.1077 - if(latch_start) 5.1078 - latch_start <= #UDLY 1'b0; 5.1079 - status1 <= #UDLY ST_READ; 5.1080 - MA_CYC_O <= #UDLY 1'b1; 5.1081 - MA_STB_O <= #UDLY 1'b1; 5.1082 - MA_ADR_O <= #UDLY reg_00_data; 5.1083 - case (reg_00_data[1:0]) 5.1084 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1085 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1086 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1087 - default: 5.1088 - MA_SEL_O <= #UDLY M_SEL_O; 5.1089 - endcase 5.1090 - set_cti_a; 5.1091 - start_flag <= #UDLY 1'b1; 5.1092 - if(!(|data_length)) 5.1093 - var_length1 <= #UDLY 1'b1; 5.1094 - else 5.1095 - var_length1 <= #UDLY 1'b0; 5.1096 - burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1097 - burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1098 - end 5.1099 - else 5.1100 - status1 <= #UDLY ST_RDFIFO; 5.1101 - end 5.1102 - else 5.1103 - status1 <= #UDLY ST_IDLE; 5.1104 - reg_interrupt1 <= #UDLY 1'b0; 5.1105 - end 5.1106 - 5.1107 - ST_WAIT_WRITE_FINISH: 5.1108 - begin 5.1109 - fifo_wr <= #UDLY 1'b0; 5.1110 - if (status2 == ST_WRITE) 5.1111 - start_flag <= #UDLY 1'b0; 5.1112 - if(end_of_transfer) 5.1113 - begin 5.1114 - if(!reg_s_con) 5.1115 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1116 - if (incr_unit == 3'b001) 5.1117 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1118 - else 5.1119 - if (incr_unit == 3'b010) 5.1120 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1121 - 5.1122 - status1 <= #UDLY ST_RDADDR; 5.1123 - burst_cnt <= #UDLY burst_size; 5.1124 - end 5.1125 - else 5.1126 - begin 5.1127 - if(burst_completed) 5.1128 - status1 <= #UDLY ST_IDLE; 5.1129 - end 5.1130 - end 5.1131 - 5.1132 - ST_RDFIFO: 5.1133 - begin 5.1134 - if(fifo_empty) 5.1135 - begin 5.1136 - status1 <= #UDLY ST_IDLE; 5.1137 - fifo_clear <= #UDLY 1'b0; 5.1138 - latch_start <= #UDLY 1'b1; 5.1139 - end 5.1140 - else 5.1141 - fifo_clear <= #UDLY !fifo_clear; 5.1142 - end 5.1143 - 5.1144 - ST_RDADDR: 5.1145 - begin 5.1146 - MA_CYC_O <= #UDLY 1'b1; 5.1147 - MA_STB_O <= #UDLY 1'b1; 5.1148 - set_cti_a; 5.1149 - status1 <= #UDLY ST_READ; 5.1150 - end 5.1151 - 5.1152 - ST_READ: 5.1153 - begin 5.1154 - write_fifo; 5.1155 - if(MA_ACK_I) 5.1156 - begin 5.1157 - if(start_flag) 5.1158 - begin 5.1159 - if(burst_cnt == 0) 5.1160 - begin 5.1161 - MA_CYC_O <= #UDLY 1'b0; 5.1162 - MA_STB_O <= #UDLY 1'b0; 5.1163 - MA_CTI_O <= #UDLY 3'h0; 5.1164 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 5.1165 - end 5.1166 - else 5.1167 - begin 5.1168 - if(burst_cnt == 1) 5.1169 - MA_CTI_O <= #UDLY 3'h7; 5.1170 - burst_cnt <= #UDLY burst_cnt - 1; 5.1171 - if(!reg_s_con) 5.1172 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1173 - if (incr_unit == 3'b001) 5.1174 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1175 - else 5.1176 - if (incr_unit == 3'b010) 5.1177 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1178 - end 5.1179 - end 5.1180 - else 5.1181 - begin 5.1182 - if(burst_cnt == 0) 5.1183 - begin 5.1184 - MA_CYC_O <= #UDLY 1'b0; 5.1185 - MA_STB_O <= #UDLY 1'b0; 5.1186 - MA_CTI_O <= #UDLY 3'h0; 5.1187 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 5.1188 - end 5.1189 - else 5.1190 - begin 5.1191 - if(burst_cnt == 1) 5.1192 - MA_CTI_O <= #UDLY 3'h7; 5.1193 - if(!reg_s_con) 5.1194 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1195 - if (incr_unit == 3'b001) 5.1196 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1197 - else 5.1198 - if (incr_unit == 3'b010) 5.1199 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1200 - burst_cnt <= #UDLY burst_cnt - 1; 5.1201 - end 5.1202 - end 5.1203 - end 5.1204 - else if(MA_RTY_I) 5.1205 - begin 5.1206 - if(var_length1) 5.1207 - begin 5.1208 - MA_CYC_O <= #UDLY 1'b0; 5.1209 - MA_STB_O <= #UDLY 1'b0; 5.1210 - MA_CTI_O <= #UDLY 3'h0; 5.1211 - status1 <= #UDLY ST_IDLE; 5.1212 - reg_status1 <= #UDLY 1'b0; 5.1213 - reg_interrupt1 <= #UDLY 1'b1; 5.1214 - start_flag <= #UDLY 1'b0; 5.1215 - end 5.1216 - end 5.1217 - else if(MA_ERR_I) 5.1218 - begin 5.1219 - MA_CYC_O <= #UDLY 1'b0; 5.1220 - MA_STB_O <= #UDLY 1'b0; 5.1221 - MA_CTI_O <= #UDLY 3'h0; 5.1222 - status1 <= #UDLY ST_IDLE; 5.1223 - reg_status1 <= #UDLY 1'b1; 5.1224 - reg_interrupt1 <= #UDLY 1'b1; 5.1225 - start_flag <= #UDLY 1'b0; 5.1226 - end 5.1227 - end 5.1228 - 5.1229 - default: 5.1230 - begin 5.1231 - status1 <= #UDLY ST_IDLE; 5.1232 - var_length1 <= #UDLY 1'b0; 5.1233 - MA_ADR_O <= #UDLY 32'h0; 5.1234 - MA_SEL_O <= #UDLY 4'b1111; 5.1235 - MA_CYC_O <= #UDLY 1'b0; 5.1236 - MA_CTI_O <= #UDLY 3'h0; 5.1237 - MA_STB_O <= #UDLY 1'b0; 5.1238 - reg_status1 <= #UDLY 1'b0; 5.1239 - reg_interrupt1 <= #UDLY 1'b0; 5.1240 - start_flag <= #UDLY 1'b0; 5.1241 - burst_size <= #UDLY 5'h0; 5.1242 - burst_cnt <= #UDLY 5'h0; 5.1243 - fifo_clear <= #UDLY 1'b0; 5.1244 - latch_start <= #UDLY 1'b0; 5.1245 - fifo_wr <= #UDLY 1'b0; 5.1246 - end 5.1247 - endcase 5.1248 - end 5.1249 - // Write Burst 5.1250 - if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ))) 5.1251 - begin 5.1252 - status2 <= #UDLY ST_WRITE_IDLE; 5.1253 - donot_start_again <= #UDLY 1'b1; 5.1254 - end 5.1255 - else 5.1256 - begin 5.1257 - case(status2) 5.1258 - ST_WRITE_IDLE: 5.1259 - begin 5.1260 - if(reg_start) 5.1261 - begin 5.1262 - MB_ADR_O <= #UDLY reg_04_data; 5.1263 - case (reg_04_data[1:0]) 5.1264 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1265 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1266 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1267 - default: 5.1268 - MB_SEL_O <= #UDLY M_SEL_O; 5.1269 - endcase 5.1270 - if(!(|data_length)) 5.1271 - var_length2 <= #UDLY 1'b1; 5.1272 - else 5.1273 - var_length2 <= #UDLY 1'b0; 5.1274 - burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1275 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1276 - if(!fifo_empty) 5.1277 - status2 <= #UDLY ST_FIFO_EMPTY; 5.1278 - else 5.1279 - donot_start_again <= #UDLY 1'b0; 5.1280 - end 5.1281 - if(fifo_empty) 5.1282 - begin 5.1283 - if(MB_ACK_I) 5.1284 - begin 5.1285 - MB_CYC_O <= #UDLY 1'b0; 5.1286 - MB_STB_O <= #UDLY 1'b0; 5.1287 - MB_CTI_O <= #UDLY 3'h0; 5.1288 - fifo_rd <= #UDLY 1'b0; 5.1289 - end 5.1290 - burst_cnt2 <= #UDLY 5'h0; 5.1291 - end 5.1292 - else 5.1293 - begin 5.1294 - if(donot_start_again) 5.1295 - begin 5.1296 - if(MB_ACK_I) 5.1297 - begin 5.1298 - if(!reg_d_con) 5.1299 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1300 - if (incr_unit == 3'b001) 5.1301 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1302 - else 5.1303 - if (incr_unit == 3'b010) 5.1304 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1305 - end 5.1306 - end 5.1307 - end 5.1308 - 5.1309 - if(!fifo_empty && !donot_start_again) 5.1310 - begin 5.1311 - if(start_flag) 5.1312 - begin 5.1313 - set_cti_b; 5.1314 - status2 <= #UDLY ST_WRITE_WAIT; 5.1315 - read_fifo; 5.1316 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1317 - end 5.1318 - else 5.1319 - begin 5.1320 - if(!reg_d_con) 5.1321 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1322 - if (incr_unit == 3'b001) 5.1323 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1324 - else 5.1325 - if (incr_unit == 3'b010) 5.1326 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1327 - status2 <= #UDLY ST_WRADDR; 5.1328 - read_fifo; 5.1329 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1330 - end 5.1331 - end 5.1332 - end_of_transfer <= #UDLY 1'b0; 5.1333 - burst_completed <= #UDLY 1'b0; 5.1334 - reg_interrupt2 <= #UDLY 1'b0; 5.1335 - end 5.1336 - 5.1337 - ST_FIFO_EMPTY: 5.1338 - begin 5.1339 - if(fifo_empty) 5.1340 - begin 5.1341 - status2 <= #UDLY ST_WRITE_IDLE; 5.1342 - donot_start_again <= #UDLY 1'b0; 5.1343 - end 5.1344 - end 5.1345 - 5.1346 - ST_WRADDR: 5.1347 - begin 5.1348 - burst_cnt2 <= #UDLY burst_size2; 5.1349 - MB_CYC_O <= #UDLY 1'b1; 5.1350 - MB_STB_O <= #UDLY 1'b1; 5.1351 - 5.1352 - if (fifo_aempty && (burst_size2 > 5'h2)) 5.1353 - begin 5.1354 - MB_CTI_O <= #UDLY 3'b000; 5.1355 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1356 - fifo_rd <= #UDLY 1'b0; 5.1357 - end 5.1358 - else 5.1359 - begin 5.1360 - set_cti_b; 5.1361 - status2 <= #UDLY ST_WRITE; 5.1362 - end 5.1363 - end 5.1364 - 5.1365 - ST_WRITE_WAIT: 5.1366 - begin 5.1367 - MB_CYC_O <= #UDLY 1'b1; 5.1368 - MB_STB_O <= #UDLY 1'b1; 5.1369 - 5.1370 - if (fifo_aempty && (burst_size2 > 5'h2)) 5.1371 - begin 5.1372 - MB_CTI_O <= #UDLY 3'b000; 5.1373 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1374 - fifo_rd <= #UDLY 1'b0; 5.1375 - end 5.1376 - else 5.1377 - begin 5.1378 - set_cti_b; 5.1379 - status2 <= #UDLY ST_WRITE; 5.1380 - end 5.1381 - end 5.1382 - 5.1383 - ST_FIFO_AEMPTY: 5.1384 - begin 5.1385 - if (MB_ACK_I) 5.1386 - begin 5.1387 - MB_CYC_O <= #UDLY 1'b0; 5.1388 - MB_STB_O <= #UDLY 1'b0; 5.1389 - 5.1390 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1391 - 5.1392 - if (!reg_d_con) 5.1393 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1394 - 5.1395 - if (incr_unit == 3'b001) 5.1396 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1397 - else 5.1398 - if (incr_unit == 3'b010) 5.1399 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1400 - end 5.1401 - 5.1402 - if (!MB_CYC_O && !fifo_aempty) 5.1403 - begin 5.1404 - status2 <= #UDLY ST_FIFO_RESUME; 5.1405 - read_fifo; 5.1406 - end 5.1407 - end 5.1408 - 5.1409 - ST_FIFO_RESUME: 5.1410 - begin 5.1411 - MB_CYC_O <= #UDLY 1'b1; 5.1412 - MB_STB_O <= #UDLY 1'b1; 5.1413 - 5.1414 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 5.1415 - begin 5.1416 - MB_CTI_O <= #UDLY 3'b000; 5.1417 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1418 - fifo_rd <= #UDLY 1'b0; 5.1419 - end 5.1420 - else 5.1421 - begin 5.1422 - set_cti_b; 5.1423 - status2 <= #UDLY ST_WRITE; 5.1424 - end 5.1425 - end 5.1426 - 5.1427 - ST_WRITE: 5.1428 - begin 5.1429 - if (MB_ACK_I) 5.1430 - begin 5.1431 - if(var_length2) 5.1432 - begin 5.1433 - if(burst_cnt2 == 0) 5.1434 - begin 5.1435 - MB_CYC_O <= #UDLY 1'b0; 5.1436 - MB_STB_O <= #UDLY 1'b0; 5.1437 - MB_CTI_O <= #UDLY 3'h0; 5.1438 - end_of_transfer <= #UDLY 1'b1; 5.1439 - status2 <= #UDLY ST_WRITE_IDLE; 5.1440 - fifo_rd <= #UDLY 1'b0; 5.1441 - burst_cnt2 <= #UDLY burst_size2; 5.1442 - end 5.1443 - else 5.1444 - begin 5.1445 - if(burst_cnt2 == 1) 5.1446 - MB_CTI_O <= #UDLY 3'h7; 5.1447 - else 5.1448 - set_cti_b; 5.1449 - if(!reg_d_con) 5.1450 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1451 - if (incr_unit == 3'b001) 5.1452 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1453 - else 5.1454 - if (incr_unit == 3'b010) 5.1455 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1456 - read_fifo; 5.1457 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1458 - end 5.1459 - end 5.1460 - else 5.1461 - begin 5.1462 - if(burst_cnt2 == 0) 5.1463 - begin 5.1464 - MB_CYC_O <= #UDLY 1'b0; 5.1465 - MB_STB_O <= #UDLY 1'b0; 5.1466 - MB_CTI_O <= #UDLY 3'h0; 5.1467 - reg_cntlg_burst <= #UDLY 1'b1; 5.1468 - status2 <= #UDLY ST_CNTLNGTH; 5.1469 - fifo_rd <= #UDLY 1'b0; 5.1470 - burst_cnt2 <= #UDLY burst_size2; 5.1471 - end 5.1472 - else 5.1473 - begin 5.1474 - if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1)) 5.1475 - MB_CTI_O <= #UDLY 3'h7; 5.1476 - else 5.1477 - set_cti_b; 5.1478 - 5.1479 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1480 - 5.1481 - if(!reg_d_con) 5.1482 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1483 - 5.1484 - if (incr_unit == 3'b001) 5.1485 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1486 - else 5.1487 - if (incr_unit == 3'b010) 5.1488 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1489 - 5.1490 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 5.1491 - begin 5.1492 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1493 - fifo_rd <= 1'b0; 5.1494 - end 5.1495 - else 5.1496 - read_fifo; 5.1497 - end 5.1498 - end 5.1499 - end 5.1500 - 5.1501 - else if(MB_RTY_I) 5.1502 - begin 5.1503 - if(var_length2) 5.1504 - begin 5.1505 - MB_CYC_O <= #UDLY 1'b0; 5.1506 - MB_STB_O <= #UDLY 1'b0; 5.1507 - MB_CTI_O <= #UDLY 3'h0; 5.1508 - status2 <= #UDLY ST_WRITE_IDLE; 5.1509 - reg_status2 <= #UDLY 1'b0; 5.1510 - reg_interrupt2 <= #UDLY 1'b1; 5.1511 - var_length2 <= #UDLY 1'b0; 5.1512 - donot_start_again <= #UDLY 1'b1; 5.1513 - fifo_rd <= #UDLY 1'b0; 5.1514 - end 5.1515 - end // if (MB_RTY_I) 5.1516 - 5.1517 - else if(MB_ERR_I) 5.1518 - begin 5.1519 - MB_CYC_O <= #UDLY 1'b0; 5.1520 - MB_STB_O <= #UDLY 1'b0; 5.1521 - MB_CTI_O <= #UDLY 3'h0; 5.1522 - status2 <= #UDLY ST_WRITE_IDLE; 5.1523 - reg_status2 <= #UDLY 1'b1; 5.1524 - reg_interrupt2 <= #UDLY 1'b1; 5.1525 - donot_start_again <= #UDLY 1'b1; 5.1526 - fifo_rd <= #UDLY 1'b0; 5.1527 - end // if (MB_ERR_I) 5.1528 - 5.1529 - end 5.1530 - 5.1531 - ST_CNTLNGTH: 5.1532 - begin 5.1533 - reg_cntlg_burst <= #UDLY 1'b0; 5.1534 - status2 <= #UDLY ST_JUSTICE; 5.1535 - end 5.1536 - 5.1537 - ST_JUSTICE: 5.1538 - begin 5.1539 - if(!(|data_length)) 5.1540 - begin 5.1541 - status2 <= #UDLY ST_WRITE_IDLE; 5.1542 - reg_status2 <= #UDLY 1'b0; 5.1543 - reg_interrupt2 <= #UDLY 1'b1; 5.1544 - burst_completed <= #UDLY 1'b1; 5.1545 - end 5.1546 - else 5.1547 - begin 5.1548 - end_of_transfer <= #UDLY 1'b1; 5.1549 - status2 <= ST_WRITE_IDLE; 5.1550 - end 5.1551 - end 5.1552 - 5.1553 - default: 5.1554 - begin 5.1555 - status2 <= #UDLY ST_WRITE_IDLE; 5.1556 - MB_ADR_O <= #UDLY 32'h0; 5.1557 - MB_SEL_O <= #UDLY 4'b1111; 5.1558 - MB_CYC_O <= #UDLY 1'b0; 5.1559 - MB_CTI_O <= #UDLY 3'h0; 5.1560 - MB_STB_O <= #UDLY 1'b0; 5.1561 - reg_status2 <= #UDLY 1'b0; 5.1562 - reg_interrupt2 <= #UDLY 1'b0; 5.1563 - reg_cntlg_burst <= #UDLY 1'b0; 5.1564 - burst_size2 <= #UDLY 5'h0; 5.1565 - burst_cnt2 <= #UDLY 5'h0; 5.1566 - fifo_rd <= #UDLY 1'b0; 5.1567 - end_of_transfer <= #UDLY 1'b0; 5.1568 - var_length2 <= #UDLY 1'b0; 5.1569 - burst_completed <= #UDLY 1'b0; 5.1570 - donot_start_again <= #UDLY 1'b0; 5.1571 - end 5.1572 - endcase 5.1573 - end 5.1574 - end 5.1575 - else begin 5.1576 - // Read/Write Normal 5.1577 - case(status) 5.1578 - 5.1579 - ST_IDLE1: 5.1580 - begin 5.1581 - if(reg_start | latch_start) 5.1582 - begin 5.1583 - if(fifo_empty) 5.1584 - begin 5.1585 - if(latch_start) 5.1586 - latch_start <= #UDLY 1'b0; 5.1587 - status <= #UDLY ST_READ1; 5.1588 - MA_CYC_O <= #UDLY 1'b1; 5.1589 - MA_STB_O <= #UDLY 1'b1; 5.1590 - MA_ADR_O <= #UDLY reg_00_data; 5.1591 - case (reg_00_data[1:0]) 5.1592 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1593 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1594 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1595 - default: 5.1596 - MA_SEL_O <= #UDLY M_SEL_O; 5.1597 - endcase 5.1598 - MB_ADR_O <= #UDLY reg_04_data; 5.1599 - case (reg_04_data[1:0]) 5.1600 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1601 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1602 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1603 - default: 5.1604 - MB_SEL_O <= #UDLY M_SEL_O; 5.1605 - endcase 5.1606 - set_cti_a; 5.1607 - start_flag <= #UDLY 1'b1; 5.1608 - if(!(|data_length)) 5.1609 - var_length <= #UDLY 1'b1; 5.1610 - else 5.1611 - var_length <= #UDLY 1'b0; 5.1612 - burst_size <= #UDLY 5'h0; 5.1613 - burst_cnt <= #UDLY 5'h0; 5.1614 - end 5.1615 - else 5.1616 - begin 5.1617 - status <= #UDLY ST_RDFIFO1; 5.1618 - end 5.1619 - end 5.1620 - else 5.1621 - begin 5.1622 - status <= #UDLY ST_IDLE1; 5.1623 - end 5.1624 - reg_interrupt_normal <= #UDLY 1'b0; 5.1625 - end 5.1626 - ST_RDFIFO1: 5.1627 - begin 5.1628 - if(fifo_empty) 5.1629 - begin 5.1630 - status <= #UDLY ST_IDLE1; 5.1631 - fifo_clear <= #UDLY 1'b0; 5.1632 - latch_start <= #UDLY 1'b1; 5.1633 - end 5.1634 - else 5.1635 - fifo_clear <= #UDLY !fifo_clear; 5.1636 - end 5.1637 - 5.1638 - ST_RDADDR1: 5.1639 - begin 5.1640 - MA_CYC_O <= #UDLY 1'b1; 5.1641 - MA_STB_O <= #UDLY 1'b1; 5.1642 - set_cti_a; 5.1643 - status <= #UDLY ST_READ1; 5.1644 - direct_data <= #UDLY 1'b1; 5.1645 - end 5.1646 - 5.1647 - ST_READ1: 5.1648 - begin 5.1649 - if(!start_flag) 5.1650 - write_fifo; 5.1651 - if(MA_ACK_I) 5.1652 - begin 5.1653 - if(start_flag) 5.1654 - begin 5.1655 - MA_CYC_O <= #UDLY 1'b0; 5.1656 - MA_STB_O <= #UDLY 1'b0; 5.1657 - MA_CTI_O <= #UDLY 3'h0; 5.1658 - MB_CYC_O <= #UDLY 1'b1; 5.1659 - MB_STB_O <= #UDLY 1'b1; 5.1660 - set_cti_b; 5.1661 - status <= #UDLY ST_WRITE1; 5.1662 - start_flag <= #UDLY 1'b0; 5.1663 - burst_cnt <= #UDLY burst_size; 5.1664 - end 5.1665 - else 5.1666 - begin 5.1667 - MA_CYC_O <= #UDLY 1'b0; 5.1668 - MA_STB_O <= #UDLY 1'b0; 5.1669 - MA_CTI_O <= #UDLY 3'h0; 5.1670 - if(!reg_d_con) 5.1671 - begin 5.1672 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1673 - if (incr_unit == 3'b001) 5.1674 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1675 - else 5.1676 - if (incr_unit == 3'b010) 5.1677 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1678 - end 5.1679 - status <= #UDLY ST_WRADDR1; 5.1680 - burst_cnt <= #UDLY burst_size; 5.1681 - end 5.1682 - end 5.1683 - else if(MA_RTY_I) 5.1684 - begin 5.1685 - if(var_length) 5.1686 - begin 5.1687 - MA_CYC_O <= #UDLY 1'b0; 5.1688 - MA_STB_O <= #UDLY 1'b0; 5.1689 - MA_CTI_O <= #UDLY 3'h0; 5.1690 - status <= #UDLY ST_IDLE1; 5.1691 - reg_status_normal <= #UDLY 1'b0; 5.1692 - reg_interrupt_normal <= #UDLY 1'b1; 5.1693 - end 5.1694 - end 5.1695 - else if(MA_ERR_I) 5.1696 - begin 5.1697 - MA_CYC_O <= #UDLY 1'b0; 5.1698 - MA_STB_O <= #UDLY 1'b0; 5.1699 - MA_CTI_O <= #UDLY 3'h0; 5.1700 - status <= #UDLY ST_IDLE1; 5.1701 - reg_status_normal <= #UDLY 1'b1; 5.1702 - reg_interrupt_normal <= #UDLY 1'b1; 5.1703 - end 5.1704 - end 5.1705 - 5.1706 - ST_WRADDR1: 5.1707 - begin 5.1708 - fifo_wr <= #UDLY 1'b0; 5.1709 - MB_CYC_O <= #UDLY 1'b1; 5.1710 - MB_STB_O <= #UDLY 1'b1; 5.1711 - burst_cnt <= #UDLY burst_size; 5.1712 - set_cti_b; 5.1713 - status <= #UDLY ST_WRITE1; 5.1714 - read_fifo; 5.1715 - end 5.1716 - 5.1717 - ST_WRITE1: 5.1718 - begin 5.1719 - if(fifo_wr) 5.1720 - fifo_wr <= #UDLY 1'b0; 5.1721 - if(MB_ACK_I) 5.1722 - begin 5.1723 - direct_data <= #UDLY 1'b0; 5.1724 - if(var_length) 5.1725 - begin 5.1726 - MB_CYC_O <= #UDLY 1'b0; 5.1727 - MB_STB_O <= #UDLY 1'b0; 5.1728 - MB_CTI_O <= #UDLY 3'h0; 5.1729 - if(!reg_s_con) 5.1730 - begin 5.1731 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1732 - if (incr_unit == 3'b001) 5.1733 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1734 - else 5.1735 - if (incr_unit == 3'b010) 5.1736 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1737 - end 5.1738 - status <= #UDLY ST_RDADDR1; 5.1739 - fifo_rd <= #UDLY 1'b0; 5.1740 - burst_cnt <= #UDLY burst_size; 5.1741 - end 5.1742 - else 5.1743 - begin 5.1744 - MB_CYC_O <= #UDLY 1'b0; 5.1745 - MB_STB_O <= #UDLY 1'b0; 5.1746 - MB_CTI_O <= #UDLY 3'h0; 5.1747 - reg_cntlg_normal <= #UDLY 1'b1; 5.1748 - status <= #UDLY ST_CNTLNGTH1; 5.1749 - fifo_rd <= #UDLY 1'b0; 5.1750 - burst_cnt <= #UDLY burst_size; 5.1751 - end 5.1752 - end 5.1753 - else if(MB_RTY_I) 5.1754 - begin 5.1755 - if(var_length) 5.1756 - begin 5.1757 - MB_CYC_O <= #UDLY 1'b0; 5.1758 - MB_STB_O <= #UDLY 1'b0; 5.1759 - MB_CTI_O <= #UDLY 3'h0; 5.1760 - status <= #UDLY ST_IDLE1; 5.1761 - reg_status_normal <= #UDLY 1'b0; 5.1762 - reg_interrupt_normal <= #UDLY 1'b1; 5.1763 - var_length <= #UDLY 1'b0; 5.1764 - fifo_rd <= #UDLY 1'b0; 5.1765 - end 5.1766 - end 5.1767 - else if(MB_ERR_I) 5.1768 - begin 5.1769 - MB_CYC_O <= #UDLY 1'b0; 5.1770 - MB_STB_O <= #UDLY 1'b0; 5.1771 - MB_CTI_O <= #UDLY 3'h0; 5.1772 - status <= #UDLY ST_IDLE1; 5.1773 - reg_status_normal <= #UDLY 1'b1; 5.1774 - reg_interrupt_normal <= #UDLY 1'b1; 5.1775 - fifo_rd <= #UDLY 1'b0; 5.1776 - end 5.1777 - end 5.1778 - 5.1779 - ST_CNTLNGTH1: 5.1780 - begin 5.1781 - reg_cntlg_normal <= #UDLY 1'b0; 5.1782 - status <= #UDLY ST_JUSTICE1; 5.1783 - end 5.1784 - 5.1785 - ST_JUSTICE1: 5.1786 - begin 5.1787 - if(!(|data_length)) 5.1788 - begin 5.1789 - status <= #UDLY ST_IDLE1; 5.1790 - reg_status_normal <= #UDLY 1'b0; 5.1791 - reg_interrupt_normal <= #UDLY 1'b1; 5.1792 - end 5.1793 - else 5.1794 - begin 5.1795 - if(!reg_s_con) 5.1796 - begin 5.1797 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1798 - if (incr_unit == 3'b001) 5.1799 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1800 - else 5.1801 - if (incr_unit == 3'b010) 5.1802 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1803 - end 5.1804 - status <= #UDLY ST_RDADDR1; 5.1805 - end 5.1806 - end 5.1807 - 5.1808 - default: 5.1809 - begin 5.1810 - status <= #UDLY ST_IDLE1; 5.1811 - var_length <= #UDLY 1'b0; 5.1812 - MA_CYC_O <= #UDLY 1'b0; 5.1813 - MA_CTI_O <= #UDLY 3'h0; 5.1814 - MB_CYC_O <= #UDLY 1'b0; 5.1815 - MB_CTI_O <= #UDLY 3'h0; 5.1816 - MA_STB_O <= #UDLY 1'b0; 5.1817 - MB_STB_O <= #UDLY 1'b0; 5.1818 - reg_status_normal <= #UDLY 1'b0; 5.1819 - reg_interrupt_normal <= #UDLY 1'b0; 5.1820 - reg_cntlg_normal <= #UDLY 1'b0; 5.1821 - burst_size <= #UDLY 3'h0; 5.1822 - burst_cnt <= #UDLY 3'h0; 5.1823 - fifo_wr <= #UDLY 1'b0; 5.1824 - fifo_rd <= #UDLY 1'b0; 5.1825 - fifo_clear <= #UDLY 1'b0; 5.1826 - latch_start <= #UDLY 1'b0; 5.1827 - direct_data <= #UDLY 1'b0; 5.1828 - end 5.1829 - endcase 5.1830 - end 5.1831 - end 5.1832 - 5.1833 - //Task for generating write enable to the FIFO 5.1834 - task write_fifo; 5.1835 - begin 5.1836 - if(MA_ACK_I) 5.1837 - begin 5.1838 - fifo_wr <= #UDLY 1'b1; 5.1839 - fifo_din <= #UDLY MA_DAT_I; 5.1840 - end 5.1841 - else 5.1842 - begin 5.1843 - fifo_wr <= #UDLY 1'b0; 5.1844 - end 5.1845 - end 5.1846 - endtask 5.1847 - 5.1848 - //Task for generating read enable signal to the FIFO 5.1849 - task read_fifo; 5.1850 - begin 5.1851 - fifo_rd <= #UDLY 1'b1; 5.1852 - end 5.1853 - endtask 5.1854 - 5.1855 - //Task for setting wishbone CTI signal for read 5.1856 - //master port depending upon whether request is for burst 5.1857 - //transfer or classic cycle. 5.1858 - task set_cti_a; 5.1859 - begin 5.1860 - if(reg_bt2) 5.1861 - begin 5.1862 - if(reg_s_con) 5.1863 - MA_CTI_O <= #UDLY 3'b001; 5.1864 - else 5.1865 - MA_CTI_O <= #UDLY 3'b010; 5.1866 - end 5.1867 - else 5.1868 - MA_CTI_O <= #UDLY 3'b000; 5.1869 - end 5.1870 - endtask 5.1871 - 5.1872 - //Task for setting wishbone CTI signal for write 5.1873 - //master port depending upon whether request is for burst 5.1874 - //transfer or classic cycle. 5.1875 - task set_cti_b; 5.1876 - begin 5.1877 - if(reg_bt2) begin 5.1878 - if(reg_d_con) 5.1879 - MB_CTI_O <= #UDLY 3'b001; 5.1880 - else 5.1881 - MB_CTI_O <= #UDLY 3'b010; 5.1882 - end else 5.1883 - MB_CTI_O <= #UDLY 3'b000; 5.1884 - end 5.1885 - endtask 5.1886 - 5.1887 - //RdEn 5.1888 - reg fifo_rd_dly; 5.1889 - always @(posedge CLK_I or posedge RST_I) 5.1890 - if(RST_I) 5.1891 - fifo_rd_dly <= #UDLY 1'b0; 5.1892 - else 5.1893 - fifo_rd_dly <= #UDLY fifo_rd; 5.1894 - 5.1895 - wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear; 5.1896 - 5.1897 + /*---------------------------------------------------------------------- 5.1898 + FIFO Logic 5.1899 + ----------------------------------------------------------------------*/ 5.1900 + reg fifo_rd_en, fifo_wr_en; 5.1901 + always @(/*AUTOSENSE*/MA_ACK_I or MA_DAT_I or MB_ACK_I 5.1902 + or fifo_aempty or fifo_empty or rstate or wburst_count 5.1903 + or wstate) 5.1904 + begin 5.1905 + if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 5.1906 + || ((wstate == WR_FIFO_CHECK) 5.1907 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.1908 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)))) 5.1909 + || ((wstate == WR_BURST) 5.1910 + && (/*(MB_CYC_O_d == 1'b0) 5.1911 + ||*/ (MB_ACK_I && (wburst_count >= 6'h1)))) 5.1912 + || ((wstate == WR_ERROR) && (fifo_empty == 1'b0)) 5.1913 + || ((wstate == WR_RETRY) && (fifo_empty == 1'b0))) 5.1914 + fifo_rd_en = 1'b1; 5.1915 + else 5.1916 + fifo_rd_en = 1'b0; 5.1917 + 5.1918 + if (MA_ACK_I 5.1919 + && ((rstate == RD_SINGLEA) || (rstate == RD_BURST))) 5.1920 + fifo_wr_en = 1'b1; 5.1921 + else 5.1922 + fifo_wr_en = 1'b0; 5.1923 + 5.1924 + fifo_din = MA_DAT_I; 5.1925 + end 5.1926 + 5.1927 generate 5.1928 if (lat_family == "SC" || lat_family == "SCM") begin 5.1929 + 5.1930 + pmi_fifo_dc 5.1931 + #(.pmi_data_width_w(MA_WB_DAT_WIDTH), 5.1932 + .pmi_data_width_r(MA_WB_DAT_WIDTH), 5.1933 + .pmi_data_depth_w(64), 5.1934 + .pmi_data_depth_r(64), 5.1935 + .pmi_full_flag(64), 5.1936 + .pmi_empty_flag(0), 5.1937 + .pmi_almost_full_flag(60), 5.1938 + .pmi_almost_empty_flag(4), 5.1939 + .pmi_regmode("noreg"), 5.1940 + .pmi_family(`LATTICE_FAMILY), 5.1941 + .module_type("pmi_fifo_dc"), 5.1942 + .pmi_implementation(FIFO_IMPLEMENTATION)) 5.1943 + dma_fifo_dc 5.1944 + ( 5.1945 + .Data(fifo_din), 5.1946 + .WrClock (CLK_I), 5.1947 + .RdClock (CLK_I), 5.1948 + .WrEn (fifo_wr_en), 5.1949 + .RdEn (fifo_rd_en), 5.1950 + .Reset (RST_I), 5.1951 + .RPReset (RST_I), 5.1952 + .Q (fifo_dout), 5.1953 + .Empty (fifo_empty), 5.1954 + .Full (), 5.1955 + .AlmostEmpty(), 5.1956 + .AlmostFull ()); 5.1957 + 5.1958 + end else if (lat_family == "MachXO2") begin 5.1959 + 5.1960 + pmi_fifo_dc 5.1961 + #(.pmi_data_width_w (MA_WB_DAT_WIDTH), 5.1962 + .pmi_data_width_r (MA_WB_DAT_WIDTH), 5.1963 + .pmi_data_depth_w (64), 5.1964 + .pmi_data_depth_r (64), 5.1965 + .pmi_full_flag (64), 5.1966 + .pmi_empty_flag (0), 5.1967 + .pmi_almost_full_flag (60), 5.1968 + .pmi_almost_empty_flag (1), 5.1969 + .pmi_regmode ("noreg"), 5.1970 + .pmi_family ("XO2"), 5.1971 + .module_type ("pmi_fifo_dc"), 5.1972 + .pmi_implementation (FIFO_IMPLEMENTATION)) 5.1973 + dma_fifo 5.1974 + (.Data (fifo_din), 5.1975 + .WrClock (CLK_I), 5.1976 + .RdClock (CLK_I), 5.1977 + .WrEn (fifo_wr_en), 5.1978 + .RdEn (fifo_rd_en), 5.1979 + .Reset (RST_I), 5.1980 + .RPReset (RST_I), 5.1981 + .Q (fifo_dout), 5.1982 + .Empty (fifo_empty), 5.1983 + .Full (), 5.1984 + .AlmostEmpty(fifo_aempty), 5.1985 + .AlmostFull ()); 5.1986 5.1987 - pmi_fifo_dc #(.pmi_data_width_w(32), 5.1988 - .pmi_data_width_r(32), 5.1989 - .pmi_data_depth_w(32), 5.1990 - .pmi_data_depth_r(32), 5.1991 - .pmi_full_flag(32), 5.1992 - .pmi_empty_flag(0), 5.1993 - .pmi_almost_full_flag(28), 5.1994 - .pmi_almost_empty_flag(4), 5.1995 - .pmi_regmode("noreg"), 5.1996 - .pmi_family(`LATTICE_FAMILY), 5.1997 - .module_type("pmi_fifo_dc"), 5.1998 - .pmi_implementation(FIFO_IMPLEMENTATION)) 5.1999 - dma_fifo_dc ( 5.2000 - .Data(fifo_din), 5.2001 - .WrClock(CLK_I), 5.2002 - .RdClock(CLK_I), 5.2003 - .WrEn (fifo_wr), 5.2004 - .RdEn (RdEn), 5.2005 - .Reset (RST_I), 5.2006 - .RPReset(RST_I), 5.2007 - .Q (fifo_dout), 5.2008 - .Empty (fifo_empty), 5.2009 - .Full (), 5.2010 - .AlmostEmpty (), 5.2011 - .AlmostFull ()); 5.2012 - 5.2013 - 5.2014 - 5.2015 end else begin 5.2016 - pmi_fifo #(.pmi_data_width(32), 5.2017 - .pmi_data_depth(32), 5.2018 - .pmi_full_flag(32), 5.2019 - .pmi_empty_flag(0), 5.2020 - .pmi_almost_full_flag(28), 5.2021 - .pmi_almost_empty_flag(1), 5.2022 - .pmi_regmode("noreg"), 5.2023 - .pmi_family(`LATTICE_FAMILY), 5.2024 - .module_type("pmi_fifo"), 5.2025 - .pmi_implementation(FIFO_IMPLEMENTATION)) 5.2026 - dma_fifo (.Data (fifo_din), 5.2027 - .Clock (CLK_I), 5.2028 - .WrEn (fifo_wr), 5.2029 - .RdEn (RdEn), 5.2030 - .Reset (RST_I), 5.2031 - .Q (fifo_dout), 5.2032 - .Empty (fifo_empty), 5.2033 - .Full (), 5.2034 - .AlmostEmpty (fifo_aempty), 5.2035 - .AlmostFull ()); 5.2036 - end 5.2037 + 5.2038 + pmi_fifo 5.2039 + #(.pmi_data_width(MA_WB_DAT_WIDTH), 5.2040 + .pmi_data_depth(64), 5.2041 + .pmi_full_flag(64), 5.2042 + .pmi_empty_flag(0), 5.2043 + .pmi_almost_full_flag(60), 5.2044 + .pmi_almost_empty_flag(1), 5.2045 + .pmi_regmode("noreg"), 5.2046 + .pmi_family(`LATTICE_FAMILY), 5.2047 + .module_type("pmi_fifo"), 5.2048 + .pmi_implementation(FIFO_IMPLEMENTATION)) 5.2049 + dma_fifo 5.2050 + (.Data (fifo_din), 5.2051 + .Clock (CLK_I), 5.2052 + .WrEn (fifo_wr_en), 5.2053 + .RdEn (fifo_rd_en), 5.2054 + .Reset (RST_I), 5.2055 + .Q (fifo_dout), 5.2056 + .Empty (fifo_empty), 5.2057 + .Full (), 5.2058 + .AlmostEmpty(fifo_aempty), 5.2059 + .AlmostFull ()); 5.2060 + 5.2061 + end 5.2062 + 5.2063 endgenerate 5.2064 5.2065 -endmodule // MASTER_CTRL 5.2066 +endmodule 5.2067 5.2068 -`endif // MASTER_CTRL_FILE 5.2069 +`endif // `ifndef MASTER_CTRL_FILE
6.1 diff -r 11aef665a5d8 -r 522426d22baa rtl/verilog/slave_reg.v 6.2 --- a/rtl/verilog/slave_reg.v Fri Aug 13 10:43:05 2010 +0100 6.3 +++ b/rtl/verilog/slave_reg.v Sat Aug 06 01:48:48 2011 +0100 6.4 @@ -1,234 +1,475 @@ 6.5 -// ============================================================================= 6.6 -// COPYRIGHT NOTICE 6.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 6.8 -// ALL RIGHTS RESERVED 6.9 -// This confidential and proprietary software may be used only as authorised by 6.10 -// a licensing agreement from Lattice Semiconductor Corporation. 6.11 -// The entire notice above must be reproduced on all authorized copies and 6.12 -// copies may only be made to the extent permitted by a licensing agreement from 6.13 -// Lattice Semiconductor Corporation. 6.14 +// ================================================================== 6.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 6.16 +// ------------------------------------------------------------------ 6.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 6.18 +// ALL RIGHTS RESERVED 6.19 +// ------------------------------------------------------------------ 6.20 +// 6.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 6.22 +// 6.23 +// Permission: 6.24 +// 6.25 +// Lattice Semiconductor grants permission to use this code 6.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 6.27 +// Open Source License Agreement. 6.28 +// 6.29 +// Disclaimer: 6.30 // 6.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 6.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 6.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 6.34 -// U.S.A email: techsupport@latticesemi.com 6.35 -// =============================================================================/ 6.36 +// Lattice Semiconductor provides no warranty regarding the use or 6.37 +// functionality of this code. It is the user's responsibility to 6.38 +// verify the user’s design for consistency and functionality through 6.39 +// the use of formal verification methods. 6.40 +// 6.41 +// -------------------------------------------------------------------- 6.42 +// 6.43 +// Lattice Semiconductor Corporation 6.44 +// 5555 NE Moore Court 6.45 +// Hillsboro, OR 97214 6.46 +// U.S.A 6.47 +// 6.48 +// TEL: 1-800-Lattice (USA and Canada) 6.49 +// 503-286-8001 (other locations) 6.50 +// 6.51 +// web: http://www.latticesemi.com/ 6.52 +// email: techsupport@latticesemi.com 6.53 +// 6.54 +// -------------------------------------------------------------------- 6.55 // FILE DETAILS 6.56 // Project : LM32 DMA Component 6.57 // File : slave_reg.v 6.58 // Title : DMA Slave controller 6.59 // Dependencies : None 6.60 +// : 6.61 // Version : 7.0 6.62 // : Initial Release 6.63 +// : 6.64 // Version : 7.0SP2, 3.0 6.65 -// 1. Read and Write channel of DMA controller are working in parallel, 6.66 -// due to that now as soon as FIFO is not empty write channel of the DMA 6.67 -// controller start writing data to the slave. 6.68 -// 2. Burst Size supported by DMA controller is increased to support bigger 6.69 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 6.70 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 6.71 -// For this Burst Size field of the control register is increased to 2 bits. 6.72 -// 3. Glitch is removed on the S_ACK_O signal. 6.73 +// : 1. Read and Write channel of DMA controller are working in 6.74 +// : parallel, due to that now as soon as FIFO is not empty 6.75 +// : write channel of the DMA controller start writing data 6.76 +// : to the slave. 6.77 +// : 2. Burst Size supported by DMA controller is increased to 6.78 +// : support bigger burst (from current value of 4 and 8 to 6.79 +// : 16 and 32). Now 4 different type of burst sizes are 6.80 +// : supported by the DMA controller 4, 8, 16 and 32. For 6.81 +// : this Burst Size field of the control register is 6.82 +// : increased to 2 bits. 6.83 +// : 3. Glitch is removed on the S_ACK_O signal. 6.84 +// : 6.85 // Version : 3.1 6.86 -// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 6.87 -// : which defines alignement of bytes in sub-word transfers. 6.88 +// : 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 6.89 +// : which defines alignement of bytes in sub-word transfers. 6.90 +// : 2. Removed glitch that did not pause the burst write when 6.91 +// : the read burst was paused by the "read slave". 6.92 +// : 6.93 +// Version : 3.2 6.94 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 6.95 +// : Read/Write Ports can be independently configured. 6.96 +// : 2. Support for burst size of 64. 6.97 +// : 6.98 +// Version : 3.3 6.99 +// : 1. Interrupt can be release by writing 0 to IE bit in the 6.100 +// : status register. 6.101 // ============================================================================= 6.102 6.103 `ifndef SLAVE_REG_FILE 6.104 `define SLAVE_REG_FILE 6.105 `include "system_conf.v" 6.106 module SLAVE_REG 6.107 - #(parameter LENGTH_WIDTH = 16, 6.108 + #(parameter S_WB_DAT_WIDTH = 32, 6.109 + parameter S_WB_ADR_WIDTH = 32, 6.110 + parameter MA_WB_DAT_WIDTH = 32, 6.111 + parameter MA_WB_ADR_WIDTH = 32, 6.112 + parameter RETRY_TIMEOUT = 16, 6.113 parameter FIFO_IMPLEMENTATION = "EBR") 6.114 - ( 6.115 - //slave port 6.116 - S_ADR_I, //32bits 6.117 - S_DAT_I, //32bits 6.118 - S_WE_I, 6.119 - S_STB_I, 6.120 - S_CYC_I, 6.121 - S_CTI_I, 6.122 - S_DAT_O, //32bits 6.123 - S_ACK_O, 6.124 - S_INT_O, 6.125 - //Master Address 6.126 -// MA_SEL_O, 6.127 -// MB_SEL_O, 6.128 - M_SEL_O, 6.129 - //internal signals 6.130 - reg_start, 6.131 - reg_status, 6.132 - reg_interrupt, 6.133 - reg_busy, 6.134 - data_length, 6.135 - reg_cntlg, 6.136 - reg_bt2,reg_bt1,reg_bt0, 6.137 - incr_unit, 6.138 - reg_s_con, 6.139 - reg_d_con, 6.140 - reg_00_data, 6.141 - reg_04_data, 6.142 - //system clock and reset 6.143 - CLK_I, 6.144 - RST_I 6.145 - ); 6.146 - 6.147 - input [31:0] S_ADR_I; 6.148 - input [31:0] S_DAT_I; //32bits 6.149 - input S_WE_I; 6.150 - input S_STB_I; 6.151 - input S_CYC_I; 6.152 - input [2:0] S_CTI_I; 6.153 - output [31:0] S_DAT_O; //32bits 6.154 - output S_ACK_O; 6.155 - output S_INT_O; //interrupt signal 6.156 - //Master Address 6.157 - output [3:0] M_SEL_O; 6.158 -// output [3:0] MA_SEL_O; 6.159 -// output [3:0] MB_SEL_O; 6.160 - //internal signals 6.161 - output reg_start; 6.162 - input reg_status; 6.163 - input reg_interrupt; 6.164 - input reg_busy; 6.165 - output [LENGTH_WIDTH-1:0] data_length; 6.166 - input reg_cntlg; 6.167 - output reg_bt2,reg_bt1,reg_bt0; 6.168 - output [2:0] incr_unit; 6.169 - output reg_s_con; 6.170 - output reg_d_con; 6.171 - output [31:0] reg_00_data; 6.172 - output [31:0] reg_04_data; 6.173 - 6.174 - //system clock and reset 6.175 - input CLK_I; 6.176 - input RST_I; 6.177 - 6.178 - parameter UDLY = 1; 6.179 - 6.180 - reg [31:0] reg_00_data; 6.181 - reg [31:0] reg_04_data; 6.182 - reg [LENGTH_WIDTH-1:0] reg_08_data; 6.183 - reg [6:0] reg_0c_data; 6.184 - 6.185 - reg [3:0] M_SEL_O; 6.186 -// wire [3:0] MA_SEL_O = M_SEL_O; 6.187 -// wire [3:0] MB_SEL_O = M_SEL_O; 6.188 - wire [LENGTH_WIDTH-1:0] data_length = reg_08_data; 6.189 - 6.190 - wire reg_bt2, reg_bt1, reg_bt0, reg_incw, reg_inchw, reg_d_con, reg_s_con; 6.191 - assign {reg_bt2,reg_bt1,reg_bt0,reg_incw,reg_inchw,reg_d_con,reg_s_con} = reg_0c_data; 6.192 - wire [2:0] incr_unit = reg_incw ? 4 : reg_inchw ? 2 : 1; 6.193 - 6.194 - wire [8:0] burst_incr_unit = reg_bt2 ? (reg_bt1 ? (reg_bt0 ? incr_unit<<5 : incr_unit<<4) : (reg_bt0 ? incr_unit<<3 : incr_unit<<2)) : incr_unit; 6.195 - reg reg_ie; 6.196 - wire [2:0] read_10_data = {reg_status,reg_ie,reg_busy}; 6.197 - 6.198 - wire reg_wr_rd = S_CYC_I && S_STB_I; 6.199 - 6.200 - wire master_idle = !reg_busy; 6.201 - reg s_ack_o_pre; 6.202 - wire S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 6.203 + ( 6.204 + input CLK_I, 6.205 + input RST_I, 6.206 + 6.207 + // Slave port 6.208 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 6.209 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 6.210 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 6.211 + input S_WE_I, 6.212 + input S_STB_I, 6.213 + input S_CYC_I, 6.214 + input [2:0] S_CTI_I, 6.215 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 6.216 + output reg S_ACK_O, 6.217 + output reg S_INT_O, 6.218 + 6.219 + output reg reg_start, 6.220 + input reg_status, 6.221 + input reg_interrupt, 6.222 + input reg_busy, 6.223 + output reg reg_bt3, reg_bt2, reg_bt1, reg_bt0, 6.224 + output reg reg_s_con, reg_d_con, 6.225 + output reg reg_incw, reg_inchw, 6.226 + output reg [7:0] reg_rdelay, 6.227 + output reg [31:0] reg_00_data, 6.228 + output reg [31:0] reg_04_data, 6.229 + output reg [31:0] reg_08_data 6.230 + ); 6.231 + 6.232 + parameter UDLY = 1; 6.233 + 6.234 + reg [31:0] reg_00_data_nxt, reg_04_data_nxt, reg_08_data_nxt; 6.235 + reg [7:0] reg_0c_data, reg_0c_data_nxt; 6.236 + 6.237 + always @(/*AUTOSENSE*/reg_0c_data) 6.238 + begin 6.239 + //reg_rdelay = reg_0c_data[23:16]; 6.240 + reg_rdelay = RETRY_TIMEOUT; 6.241 + reg_bt3 = reg_0c_data[7]; 6.242 + reg_bt2 = reg_0c_data[6]; 6.243 + reg_bt1 = reg_0c_data[5]; 6.244 + reg_bt0 = reg_0c_data[4]; 6.245 + reg_incw = reg_0c_data[3]; 6.246 + reg_inchw = reg_0c_data[2]; 6.247 + reg_d_con = reg_0c_data[1]; 6.248 + reg_s_con = reg_0c_data[0]; 6.249 + end 6.250 + 6.251 + reg [2:0] read_10_data; 6.252 + reg reg_ie; 6.253 + always @(/*AUTOSENSE*/reg_busy or reg_ie or reg_status) 6.254 + begin 6.255 + read_10_data[2] = reg_status; 6.256 + read_10_data[1] = reg_ie; 6.257 + read_10_data[0] = reg_busy; 6.258 + end 6.259 + 6.260 + wire master_idle, reg_wr_rd, reg_wr, reg_rd; 6.261 + assign master_idle = ~reg_busy; 6.262 + assign reg_wr_rd = S_CYC_I & S_STB_I; 6.263 + assign reg_wr = reg_wr_rd & master_idle & S_WE_I & S_ACK_O; 6.264 + assign reg_rd = reg_wr_rd & ~S_WE_I & S_ACK_O; 6.265 + 6.266 + reg s_ack_o_pre, s_ack_o_pre_nxt; 6.267 + always @(/*AUTOSENSE*/S_CYC_I or S_STB_I or S_WE_I or master_idle 6.268 + or reg_wr_rd or s_ack_o_pre) 6.269 + begin 6.270 + if ((s_ack_o_pre == 1'b0) 6.271 + && ((master_idle && reg_wr_rd) 6.272 + || ((master_idle == 1'b0) && reg_wr_rd && (S_WE_I == 1'b0)))) 6.273 + s_ack_o_pre_nxt = 1'b1; 6.274 + else 6.275 + s_ack_o_pre_nxt = 1'b0; 6.276 + 6.277 + S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 6.278 + end 6.279 6.280 always @(posedge CLK_I or posedge RST_I) 6.281 - if(RST_I) 6.282 - s_ack_o_pre <= #UDLY 1'b0; 6.283 - else if(((master_idle && reg_wr_rd) || (!master_idle && reg_wr_rd && !S_WE_I)) && (!s_ack_o_pre)) 6.284 - s_ack_o_pre <= #UDLY 1'b1; 6.285 - else 6.286 - s_ack_o_pre <= #UDLY 1'b0; 6.287 - 6.288 - 6.289 - //register write and read 6.290 - wire reg_wr = reg_wr_rd && S_WE_I && master_idle && S_ACK_O; 6.291 - wire reg_rd = reg_wr_rd && !S_WE_I && S_ACK_O; 6.292 - 6.293 - wire dw00_cs = (!(|S_ADR_I[5:2])); 6.294 - wire dw04_cs = (S_ADR_I[5:2] == 4'h1); 6.295 - wire dw08_cs = (S_ADR_I[5:2] == 4'h2); 6.296 - wire dw0c_cs = (S_ADR_I[5:2] == 4'h3); 6.297 - wire dw10_cs = (S_ADR_I[5:2] == 4'h4); 6.298 + if (RST_I) 6.299 + s_ack_o_pre <= #UDLY 1'b0; 6.300 + else 6.301 + s_ack_o_pre <= #UDLY s_ack_o_pre_nxt; 6.302 + 6.303 + wire dw00_cs, dw04_cs, dw08_cs, dw0c_cs, dw10_cs; 6.304 + assign dw00_cs = (S_ADR_I[5:2] == 4'h0); 6.305 + assign dw04_cs = (S_ADR_I[5:2] == 4'h1); 6.306 + assign dw08_cs = (S_ADR_I[5:2] == 4'h2); 6.307 + assign dw0c_cs = (S_ADR_I[5:2] == 4'h3); 6.308 + assign dw10_cs = (S_ADR_I[5:2] == 4'h4); 6.309 + 6.310 + wire [31:0] S_DAT_O_int = (dw00_cs 6.311 + ? reg_00_data 6.312 + : (dw04_cs 6.313 + ? reg_04_data 6.314 + : (dw08_cs 6.315 + ? reg_08_data 6.316 + : (dw0c_cs 6.317 + ? {4{reg_0c_data}} 6.318 + : (dw10_cs 6.319 + ? {4{5'h0,read_10_data}} 6.320 + : 32'h0))))); 6.321 + generate 6.322 + if (S_WB_DAT_WIDTH == 8) begin 6.323 + 6.324 + assign S_DAT_O = ((S_ADR_I[1:0] == 2'b00) 6.325 + ? S_DAT_O_int[31:24] 6.326 + : ((S_ADR_I[1:0] == 2'b01) 6.327 + ? S_DAT_O_int[23:16] 6.328 + : ((S_ADR_I[1:0] == 2'b10) 6.329 + ? S_DAT_O_int[15:8] 6.330 + : S_DAT_O_int[7:0]))); 6.331 + 6.332 + end 6.333 + else begin 6.334 + 6.335 + assign S_DAT_O = S_DAT_O_int; 6.336 + 6.337 + end 6.338 + endgenerate 6.339 + 6.340 + 6.341 + 6.342 + // Interrupt 6.343 + generate 6.344 + if (S_WB_DAT_WIDTH == 8) begin 6.345 + 6.346 + always @(posedge CLK_I or posedge RST_I) 6.347 + begin 6.348 + if(RST_I) 6.349 + S_INT_O <= #UDLY 1'b0; 6.350 + else if(reg_interrupt && reg_ie) 6.351 + S_INT_O <= #UDLY 1'b1; 6.352 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[1] == 1'b0)))) 6.353 + S_INT_O <= #UDLY 1'b0; 6.354 + end 6.355 + 6.356 + end 6.357 + else begin 6.358 + 6.359 + always @(posedge CLK_I or posedge RST_I) 6.360 + begin 6.361 + if(RST_I) 6.362 + S_INT_O <= #UDLY 1'b0; 6.363 + else if(reg_interrupt && reg_ie) 6.364 + S_INT_O <= #UDLY 1'b1; 6.365 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[25] == 1'b0)))) 6.366 + S_INT_O <= #UDLY 1'b0; 6.367 + end 6.368 + 6.369 + end 6.370 + endgenerate 6.371 + 6.372 + // reg_00 6.373 + generate 6.374 + if (S_WB_DAT_WIDTH == 8) begin 6.375 6.376 - //S_DAT_O 6.377 - wire [31:0] S_DAT_O = dw00_cs ? reg_00_data : 6.378 - dw04_cs ? reg_04_data : 6.379 - dw08_cs ? reg_08_data : 6.380 - dw0c_cs ? {24'h0,1'h0,reg_0c_data} : 6.381 - dw10_cs ? {24'h0,5'h0,read_10_data} : 32'h0; 6.382 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw00_cs 6.383 + or reg_00_data or reg_wr) 6.384 + begin 6.385 + if (dw00_cs && reg_wr) begin 6.386 + casez (S_ADR_I[1:0]) 6.387 + 2'b00: reg_00_data_nxt = { S_DAT_I[7:0], reg_00_data[23: 0]}; 6.388 + 2'b01: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[7:0], reg_00_data[15: 0]}; 6.389 + 2'b10: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[7:0], reg_00_data[ 7: 0]}; 6.390 + 2'b11: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[7:0] }; 6.391 + 6.392 + default: 6.393 + reg_00_data_nxt = reg_00_data; 6.394 + endcase 6.395 + end 6.396 + else 6.397 + reg_00_data_nxt = reg_00_data; 6.398 + end 6.399 + 6.400 + end 6.401 + else begin 6.402 + 6.403 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw00_cs 6.404 + or reg_00_data or reg_wr) 6.405 + begin 6.406 + if (dw00_cs && reg_wr) begin 6.407 + casez (S_SEL_I) 6.408 + 4'b1000: reg_00_data_nxt = { S_DAT_I[31:24], reg_00_data[23:0]}; 6.409 + 4'b0100: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[23:16], reg_00_data[15:0]}; 6.410 + 4'b0010: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[15: 8], reg_00_data[ 7:0]}; 6.411 + 4'b0001: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[ 7: 0] }; 6.412 + 4'b1111: reg_00_data_nxt = S_DAT_I[31: 0] ; 6.413 + 6.414 + default: 6.415 + reg_00_data_nxt = reg_00_data; 6.416 + endcase 6.417 + end 6.418 + else 6.419 + reg_00_data_nxt = reg_00_data; 6.420 + end 6.421 + 6.422 + end 6.423 + endgenerate 6.424 + 6.425 + always @(posedge CLK_I or posedge RST_I) 6.426 + if (RST_I) 6.427 + reg_00_data <= #UDLY 32'b0; 6.428 + else 6.429 + reg_00_data <= #UDLY reg_00_data_nxt; 6.430 + 6.431 + 6.432 + 6.433 + // reg_04 6.434 + generate 6.435 + if (S_WB_DAT_WIDTH == 8) begin 6.436 6.437 - always @(posedge CLK_I or posedge RST_I) 6.438 - if(RST_I) 6.439 - M_SEL_O <= #UDLY 4'h0; 6.440 - else if(data_length < incr_unit) 6.441 - case(data_length[2:0]) 6.442 - 1: M_SEL_O <= #UDLY 4'h8; 6.443 - 2: M_SEL_O <= #UDLY 4'hc; 6.444 - 3: M_SEL_O <= #UDLY 4'he; 6.445 - default:M_SEL_O <= #UDLY 4'hf; 6.446 - endcase 6.447 - else 6.448 - case(incr_unit) 6.449 - 1: M_SEL_O <= #UDLY 4'h8; 6.450 - 2: M_SEL_O <= #UDLY 4'hc; 6.451 - 4: M_SEL_O <= #UDLY 4'hf; 6.452 - default:M_SEL_O <= #UDLY 4'hf; 6.453 - endcase 6.454 - //interrupt 6.455 - reg S_INT_O; 6.456 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw04_cs 6.457 + or reg_04_data or reg_wr) 6.458 + begin 6.459 + if (dw04_cs && reg_wr) begin 6.460 + casez (S_ADR_I[1:0]) 6.461 + 2'b00: reg_04_data_nxt = { S_DAT_I[7:0], reg_04_data[23: 0]}; 6.462 + 2'b01: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[7:0], reg_04_data[15: 0]}; 6.463 + 2'b10: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[7:0], reg_04_data[ 7: 0]}; 6.464 + 2'b11: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[7:0] }; 6.465 + 6.466 + default: 6.467 + reg_04_data_nxt = reg_04_data; 6.468 + endcase 6.469 + end 6.470 + else 6.471 + reg_04_data_nxt = reg_04_data; 6.472 + end 6.473 + 6.474 + end 6.475 + else begin 6.476 + 6.477 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw04_cs 6.478 + or reg_04_data or reg_wr) 6.479 + begin 6.480 + if (dw04_cs && reg_wr) begin 6.481 + casez (S_SEL_I) 6.482 + 4'b1000: reg_04_data_nxt = { S_DAT_I[31:24], reg_04_data[23:0]}; 6.483 + 4'b0100: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[23:16], reg_04_data[15:0]}; 6.484 + 4'b0010: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[15: 8], reg_04_data[ 7:0]}; 6.485 + 4'b0001: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[ 7: 0] }; 6.486 + 4'b1111: reg_04_data_nxt = { S_DAT_I[31: 0] }; 6.487 + 6.488 + default: 6.489 + reg_04_data_nxt = reg_04_data; 6.490 + endcase 6.491 + end 6.492 + else 6.493 + reg_04_data_nxt = reg_04_data; 6.494 + end 6.495 + 6.496 + end 6.497 + endgenerate 6.498 + 6.499 always @(posedge CLK_I or posedge RST_I) 6.500 - if(RST_I) 6.501 - S_INT_O <= #UDLY 1'b0; 6.502 - else if(reg_interrupt && reg_ie) 6.503 - S_INT_O <= #UDLY 1'b1; 6.504 - else if(dw10_cs && reg_rd) 6.505 - S_INT_O <= #UDLY 1'b0; 6.506 + if (RST_I) 6.507 + reg_04_data <= #UDLY 32'b0; 6.508 + else 6.509 + reg_04_data <= #UDLY reg_04_data_nxt; 6.510 + 6.511 + 6.512 + 6.513 + // reg_08 6.514 + generate 6.515 + if (S_WB_DAT_WIDTH == 8) begin 6.516 6.517 - //reg_00 6.518 - always @(posedge CLK_I or posedge RST_I) 6.519 - if(RST_I) 6.520 - reg_00_data <= #UDLY 32'h0; 6.521 - else if(dw00_cs && reg_wr) 6.522 - reg_00_data <= #UDLY S_DAT_I; 6.523 - 6.524 - //reg_04 6.525 - always @(posedge CLK_I or posedge RST_I) 6.526 - if(RST_I) 6.527 - reg_04_data <= #UDLY 32'h0; 6.528 - else if(dw04_cs && reg_wr) 6.529 - reg_04_data <= #UDLY S_DAT_I; 6.530 - 6.531 - //reg_08 6.532 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw08_cs 6.533 + or reg_08_data or reg_wr) 6.534 + if (dw08_cs && reg_wr) begin 6.535 + casez (S_ADR_I[1:0]) 6.536 + 2'b00: reg_08_data_nxt = { S_DAT_I[7:0], reg_08_data[23: 0]}; 6.537 + 2'b01: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[7:0], reg_08_data[15: 0]}; 6.538 + 2'b10: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[7:0], reg_08_data[ 7: 0]}; 6.539 + 2'b11: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[7:0] }; 6.540 + 6.541 + default: 6.542 + reg_08_data_nxt = reg_08_data; 6.543 + endcase 6.544 + end 6.545 + 6.546 + end 6.547 + else begin 6.548 + 6.549 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw08_cs 6.550 + or reg_08_data or reg_wr) 6.551 + if (dw08_cs && reg_wr) begin 6.552 + casez (S_SEL_I) 6.553 + 4'b1000: reg_08_data_nxt = { S_DAT_I[31:24], reg_08_data[23:0]}; 6.554 + 4'b0100: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[23:16], reg_08_data[15:0]}; 6.555 + 4'b0010: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[15: 8], reg_08_data[ 7:0]}; 6.556 + 4'b0001: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[ 7: 0] }; 6.557 + 4'b1111: reg_08_data_nxt = { S_DAT_I[31: 0] }; 6.558 + 6.559 + default: 6.560 + reg_08_data_nxt = reg_08_data; 6.561 + endcase 6.562 + end 6.563 + 6.564 + end 6.565 + endgenerate 6.566 + 6.567 always @(posedge CLK_I or posedge RST_I) 6.568 - if(RST_I) 6.569 - reg_08_data <= #UDLY 32'h0; 6.570 - else if(reg_cntlg) 6.571 - reg_08_data <= #UDLY (reg_08_data < burst_incr_unit) ? 'h0 : (reg_08_data - burst_incr_unit); 6.572 - else if(dw08_cs && reg_wr) 6.573 - reg_08_data <= #UDLY S_DAT_I; 6.574 - 6.575 - //reg_0c 6.576 + if (RST_I) 6.577 + reg_08_data <= #UDLY 0; 6.578 + else 6.579 + reg_08_data <= #UDLY reg_08_data_nxt[31:0]; 6.580 + 6.581 + 6.582 + 6.583 + // reg_0c 6.584 + generate 6.585 + if (S_WB_DAT_WIDTH == 8) begin 6.586 + 6.587 + always @(/*AUTOSENSE*/S_DAT_I or dw0c_cs or reg_0c_data 6.588 + or reg_wr) 6.589 + if (dw0c_cs && reg_wr) 6.590 + reg_0c_data_nxt = S_DAT_I[7:0]; 6.591 + else 6.592 + reg_0c_data_nxt = reg_0c_data; 6.593 + 6.594 + end 6.595 + else begin 6.596 + 6.597 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw0c_cs 6.598 + or reg_0c_data or reg_wr) 6.599 + if (dw0c_cs && reg_wr) 6.600 + reg_0c_data_nxt = S_DAT_I[31:24]; 6.601 + else 6.602 + reg_0c_data_nxt = reg_0c_data; 6.603 + 6.604 + end 6.605 + endgenerate 6.606 + 6.607 always @(posedge CLK_I or posedge RST_I) 6.608 - if(RST_I) 6.609 - reg_0c_data <= #UDLY 7'h0; 6.610 - else if(dw0c_cs && reg_wr) 6.611 - reg_0c_data <= #UDLY S_DAT_I[6:0]; 6.612 - 6.613 - //reg_10 6.614 - reg reg_start; 6.615 + if (RST_I) 6.616 + reg_0c_data <= #UDLY 8'b0; 6.617 + else 6.618 + reg_0c_data <= #UDLY reg_0c_data_nxt; 6.619 + 6.620 + 6.621 + 6.622 + // reg_10 6.623 + reg reg_ie_nxt, reg_start_nxt; 6.624 + generate 6.625 + if (S_WB_DAT_WIDTH == 8) begin 6.626 + 6.627 + always @(/*AUTOSENSE*/S_DAT_I or dw10_cs or reg_ie or reg_wr) 6.628 + if (dw10_cs && reg_wr) 6.629 + begin 6.630 + reg_ie_nxt = S_DAT_I[1]; 6.631 + reg_start_nxt = S_DAT_I[3]; 6.632 + end 6.633 + else 6.634 + begin 6.635 + reg_ie_nxt = reg_ie; 6.636 + reg_start_nxt = 1'b0; 6.637 + end 6.638 + 6.639 + end 6.640 + else begin 6.641 + 6.642 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw10_cs or reg_ie 6.643 + or reg_wr) 6.644 + if (dw10_cs && reg_wr) 6.645 + begin 6.646 + reg_ie_nxt = S_DAT_I[25]; 6.647 + reg_start_nxt = S_DAT_I[27]; 6.648 + end 6.649 + else 6.650 + begin 6.651 + reg_ie_nxt = reg_ie; 6.652 + reg_start_nxt = 1'b0; 6.653 + end 6.654 + 6.655 + end 6.656 + endgenerate 6.657 + 6.658 always @(posedge CLK_I or posedge RST_I) 6.659 - if(RST_I) 6.660 + if (RST_I) 6.661 begin 6.662 - reg_ie <= #UDLY 1'b0; 6.663 - reg_start <= #UDLY 1'b0; 6.664 - end 6.665 - else if(dw10_cs && reg_wr) 6.666 + reg_ie <= #UDLY 1'b0; 6.667 + reg_start <= #UDLY 1'b0; 6.668 + end 6.669 + else 6.670 begin 6.671 - reg_ie <= #UDLY S_DAT_I[1]; 6.672 - reg_start <= #UDLY S_DAT_I[3]; 6.673 + reg_ie <= #UDLY reg_ie_nxt; 6.674 + reg_start <= #UDLY reg_start_nxt; 6.675 end 6.676 - else 6.677 - begin 6.678 - reg_start <= #UDLY 1'b0; 6.679 - end 6.680 + 6.681 endmodule // SLAVE_REG 6.682 `endif // SLAVE_REG_FILE
7.1 diff -r 11aef665a5d8 -r 522426d22baa rtl/verilog/wb_dma_ctrl.v 7.2 --- a/rtl/verilog/wb_dma_ctrl.v Fri Aug 13 10:43:05 2010 +0100 7.3 +++ b/rtl/verilog/wb_dma_ctrl.v Sat Aug 06 01:48:48 2011 +0100 7.4 @@ -1,237 +1,245 @@ 7.5 -// ============================================================================= 7.6 -// COPYRIGHT NOTICE 7.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 7.8 -// ALL RIGHTS RESERVED 7.9 -// This confidential and proprietary software may be used only as authorised by 7.10 -// a licensing agreement from Lattice Semiconductor Corporation. 7.11 -// The entire notice above must be reproduced on all authorized copies and 7.12 -// copies may only be made to the extent permitted by a licensing agreement from 7.13 -// Lattice Semiconductor Corporation. 7.14 +// ================================================================== 7.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 7.16 +// ------------------------------------------------------------------ 7.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 7.18 +// ALL RIGHTS RESERVED 7.19 +// ------------------------------------------------------------------ 7.20 +// 7.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 7.22 +// 7.23 +// Permission: 7.24 +// 7.25 +// Lattice Semiconductor grants permission to use this code 7.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 7.27 +// Open Source License Agreement. 7.28 +// 7.29 +// Disclaimer: 7.30 // 7.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 7.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 7.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 7.34 -// U.S.A email: techsupport@latticesemi.com 7.35 -// =============================================================================/ 7.36 +// Lattice Semiconductor provides no warranty regarding the use or 7.37 +// functionality of this code. It is the user's responsibility to 7.38 +// verify the user’s design for consistency and functionality through 7.39 +// the use of formal verification methods. 7.40 +// 7.41 +// -------------------------------------------------------------------- 7.42 +// 7.43 +// Lattice Semiconductor Corporation 7.44 +// 5555 NE Moore Court 7.45 +// Hillsboro, OR 97214 7.46 +// U.S.A 7.47 +// 7.48 +// TEL: 1-800-Lattice (USA and Canada) 7.49 +// 503-286-8001 (other locations) 7.50 +// 7.51 +// web: http://www.latticesemi.com/ 7.52 +// email: techsupport@latticesemi.com 7.53 +// 7.54 +// -------------------------------------------------------------------- 7.55 // FILE DETAILS 7.56 // Project : LM32 DMA Component 7.57 // File : wb_dma_ctrl.v 7.58 // Title : DMA controller top file 7.59 // Dependencies : None 7.60 +// : 7.61 // Version : 7.0 7.62 // : Initial Release 7.63 +// : 7.64 // Version : 7.0SP2, 3.0 7.65 -// 1. Read and Write channel of DMA controller are working in parallel, 7.66 -// due to that now as soon as FIFO is not empty write channel of the DMA 7.67 -// controller start writing data to the slave. 7.68 -// 2. Burst Size supported by DMA controller is increased to support bigger 7.69 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 7.70 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 7.71 -// For this Burst Size field of the control register is increased to 2 bits. 7.72 -// 3. Glitch is removed on the S_ACK_O signal. 7.73 +// : 1. Read and Write channel of DMA controller are working in 7.74 +// : parallel, due to that now as soon as FIFO is not empty 7.75 +// : write channel of the DMA controller start writing data 7.76 +// : to the slave. 7.77 +// : 2. Burst Size supported by DMA controller is increased to 7.78 +// : support bigger burst (from current value of 4 and 8 to 7.79 +// : 16 and 32). Now 4 different type of burst sizes are 7.80 +// : supported by the DMA controller 4, 8, 16 and 32. For 7.81 +// : this Burst Size field of the control register is 7.82 +// : increased to 2 bits. 7.83 +// : 3. Glitch is removed on the S_ACK_O signal. 7.84 +// : 7.85 // Version : 3.1 7.86 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 7.87 // : which defines alignement of bytes in sub-word transfers. 7.88 +// : 7.89 +// Version : 3.2 7.90 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 7.91 +// : Read/Write Ports can be independently configured. 7.92 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 7.93 +// : retry results in the current burst or classic cycle 7.94 +// : being issued again after a retry timeout. 7.95 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 7.96 +// : results in the current dma transfer being terminated 7.97 +// : and the error is updated within the STATUS CSR. 7.98 +// : 4. Support for burst size of 64. 7.99 // ============================================================================= 7.100 7.101 `ifndef WB_DMA_CTRL_FILE 7.102 `define WB_DMA_CTRL_FILE 7.103 `include "system_conf.v" 7.104 -module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16, 7.105 - parameter FIFO_IMPLEMENTATION = "EBR") 7.106 -( 7.107 - //master read port 7.108 - MA_ADR_O, //32bits 7.109 - MA_WE_O, 7.110 - MA_SEL_O, //4bits 7.111 - MA_STB_O, 7.112 - MA_CYC_O, 7.113 - MA_LOCK_O, 7.114 - MA_CTI_O, 7.115 - MA_BTE_O, 7.116 - MA_DAT_I, //32bits 7.117 - MA_DAT_O, //32bits 7.118 - MA_ACK_I, 7.119 - MA_ERR_I, 7.120 - MA_RTY_I, 7.121 - //master write port 7.122 - MB_ADR_O, //32bits 7.123 - MB_DAT_O, //32bits 7.124 - MB_WE_O, 7.125 - MB_SEL_O, //4bits 7.126 - MB_STB_O, 7.127 - MB_CYC_O, 7.128 - MB_LOCK_O, 7.129 - MB_CTI_O, 7.130 - MB_BTE_O, 7.131 - MB_DAT_I, //32bits 7.132 - MB_ACK_I, 7.133 - MB_ERR_I, 7.134 - MB_RTY_I, 7.135 - //slave port 7.136 - S_ADR_I, //32bits 7.137 - S_DAT_I, //32bits 7.138 - S_WE_I, 7.139 - S_STB_I, 7.140 - S_CYC_I, 7.141 - S_SEL_I, 7.142 - S_LOCK_I, 7.143 - S_CTI_I, 7.144 - S_BTE_I, 7.145 - S_DAT_O, //32bits 7.146 - S_ACK_O, 7.147 - S_ERR_O, 7.148 - S_RTY_O, 7.149 - S_INT_O, 7.150 - //system clock and reset 7.151 - CLK_I, 7.152 - RST_I 7.153 - ); 7.154 - //master read port 7.155 - output [31:0] MA_ADR_O; //32bits 7.156 - output MA_WE_O; 7.157 - output [3:0] MA_SEL_O; //4bits 7.158 - output MA_STB_O; 7.159 - output MA_CYC_O; 7.160 - output MA_LOCK_O; 7.161 - output [2:0] MA_CTI_O; 7.162 - output [1:0] MA_BTE_O; 7.163 - output [31:0] MA_DAT_O; //32bits 7.164 - input [31:0] MA_DAT_I; //32bits 7.165 - input MA_ACK_I; 7.166 - input MA_ERR_I; 7.167 - input MA_RTY_I; 7.168 - //master write port 7.169 - output [31:0] MB_ADR_O; //32bits 7.170 - output [31:0] MB_DAT_O; //32bits 7.171 - output MB_WE_O; 7.172 - output [3:0] MB_SEL_O; //4bits 7.173 - output MB_STB_O; 7.174 - output MB_CYC_O; 7.175 - output [2:0] MB_CTI_O; 7.176 - output MB_LOCK_O; 7.177 - output [1:0] MB_BTE_O; 7.178 - input [31:0] MB_DAT_I; //32bits 7.179 - input MB_ACK_I; 7.180 - input MB_ERR_I; 7.181 - input MB_RTY_I; 7.182 - //slave port 7.183 - input [31:0] S_ADR_I; //32bits 7.184 - input [31:0] S_DAT_I; //32bits 7.185 - input S_WE_I; 7.186 - input S_STB_I; 7.187 - input S_CYC_I; 7.188 - input [2:0] S_CTI_I; 7.189 - input [1:0] S_BTE_I; 7.190 - input [3:0] S_SEL_I; 7.191 - input S_LOCK_I; 7.192 - output [31:0] S_DAT_O; //32bits 7.193 - output S_ACK_O; 7.194 - output S_ERR_O; 7.195 - output S_RTY_O; 7.196 - output S_INT_O; 7.197 - //system clock and reset 7.198 - input CLK_I; 7.199 - input RST_I; 7.200 - 7.201 - wire [31:0] MA_DAT_O = 0; 7.202 - wire [1:0] MA_BTE_O = 0; 7.203 - wire MA_LOCK_O; 7.204 +module wb_dma_ctrl 7.205 + #(parameter S_WB_DAT_WIDTH = 32, 7.206 + parameter S_WB_ADR_WIDTH = 32, 7.207 + parameter MA_WB_DAT_WIDTH = 32, 7.208 + parameter MA_WB_ADR_WIDTH = 32, 7.209 + parameter MB_WB_DAT_WIDTH = 32, 7.210 + parameter MB_WB_ADR_WIDTH = 32, 7.211 + parameter RETRY_TIMEOUT = 16, 7.212 + parameter FIFO_IMPLEMENTATION = "EBR") 7.213 + ( 7.214 + // master read port 7.215 + output [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 7.216 + output MA_WE_O, 7.217 + output [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 7.218 + output MA_STB_O, 7.219 + output MA_CYC_O, 7.220 + output MA_LOCK_O, 7.221 + output [2:0] MA_CTI_O, 7.222 + output [1:0] MA_BTE_O, 7.223 + output [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 7.224 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 7.225 + input MA_ACK_I, 7.226 + input MA_ERR_I, 7.227 + input MA_RTY_I, 7.228 + // master write port 7.229 + output [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 7.230 + output [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 7.231 + output MB_WE_O, 7.232 + output [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 7.233 + output MB_STB_O, 7.234 + output MB_CYC_O, 7.235 + output MB_LOCK_O, 7.236 + output [2:0] MB_CTI_O, 7.237 + output [1:0] MB_BTE_O, 7.238 + input [MB_WB_DAT_WIDTH-1:0] MB_DAT_I, 7.239 + input MB_ACK_I, 7.240 + input MB_ERR_I, 7.241 + input MB_RTY_I, 7.242 + // slave port 7.243 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 7.244 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 7.245 + input S_WE_I, 7.246 + input S_STB_I, 7.247 + input S_CYC_I, 7.248 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 7.249 + input S_LOCK_I, 7.250 + input [2:0] S_CTI_I, 7.251 + input [1:0] S_BTE_I, 7.252 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 7.253 + output S_ACK_O, 7.254 + output S_ERR_O, 7.255 + output S_RTY_O, 7.256 + output S_INT_O, 7.257 + // system clock and reset 7.258 + input CLK_I, 7.259 + input RST_I 7.260 + ); 7.261 + 7.262 + assign MA_BTE_O = 0; 7.263 + assign MB_BTE_O = 0; 7.264 + assign S_ERR_O = 0; 7.265 + assign S_RTY_O = 0; 7.266 + 7.267 + wire [31:0] reg_00_data; 7.268 + wire [31:0] reg_04_data; 7.269 + wire [31:0] reg_08_data; 7.270 + wire [7:0] reg_rdelay; 7.271 7.272 - wire [1:0] MB_BTE_O = 0; 7.273 - wire MB_LOCK_O; 7.274 - 7.275 - wire S_ERR_O = 0; 7.276 - wire S_RTY_O = 0; 7.277 - 7.278 - wire [LENGTH_WIDTH-1:0] data_length;//read back data 7.279 - wire [2:0] incr_unit; 7.280 - wire [31:0] reg_00_data; 7.281 - wire [31:0] reg_04_data; 7.282 - wire [3:0] M_SEL_O; 7.283 - 7.284 - //slave port:master write/read data to/from register file. 7.285 - SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH), 7.286 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG( 7.287 - .S_ADR_I (S_ADR_I ), 7.288 - .S_DAT_I (S_DAT_I ), 7.289 - .S_WE_I (S_WE_I ), 7.290 - .S_STB_I (S_STB_I ), 7.291 - .S_CYC_I (S_CYC_I ), 7.292 - .S_CTI_I (S_CTI_I ), 7.293 - .S_DAT_O (S_DAT_O ), 7.294 - .S_ACK_O (S_ACK_O ), 7.295 - .S_INT_O (S_INT_O ), 7.296 - //Master Addr 7.297 - .M_SEL_O (M_SEL_O ), 7.298 -// .MA_SEL_O (MA_SEL_O ), 7.299 -// .MB_SEL_O (MB_SEL_O ), 7.300 - //internal signals 7.301 - .reg_start (reg_start ), 7.302 - .reg_status (reg_status ), 7.303 - .reg_interrupt (reg_interrupt ), 7.304 - .reg_busy (reg_busy ), 7.305 - .data_length (data_length ), 7.306 - .reg_cntlg (reg_cntlg ), 7.307 - .reg_bt2 (reg_bt2 ), 7.308 - .reg_bt1 (reg_bt1 ), 7.309 - .reg_bt0 (reg_bt0 ), 7.310 - .reg_s_con (reg_s_con ), 7.311 - .reg_d_con (reg_d_con ), 7.312 - .incr_unit (incr_unit ), 7.313 - .reg_00_data (reg_00_data ), 7.314 - .reg_04_data (reg_04_data ), 7.315 - //system clock and reset 7.316 - .CLK_I (CLK_I ), 7.317 - .RST_I (RST_I ) 7.318 - ); 7.319 + // slave port:master write/read data to/from register file. 7.320 + SLAVE_REG 7.321 + #(.S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 7.322 + .S_WB_ADR_WIDTH (S_WB_ADR_WIDTH), 7.323 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 7.324 + ) 7.325 + SLAVE_REG 7.326 + ( 7.327 + .S_ADR_I (S_ADR_I ), 7.328 + .S_DAT_I (S_DAT_I ), 7.329 + .S_SEL_I (S_SEL_I ), 7.330 + .S_WE_I (S_WE_I ), 7.331 + .S_STB_I (S_STB_I ), 7.332 + .S_CYC_I (S_CYC_I ), 7.333 + .S_CTI_I (S_CTI_I ), 7.334 + .S_DAT_O (S_DAT_O ), 7.335 + .S_ACK_O (S_ACK_O ), 7.336 + .S_INT_O (S_INT_O ), 7.337 + // internal signals 7.338 + .reg_start (reg_start ), 7.339 + .reg_status (reg_status ), 7.340 + .reg_interrupt (reg_interrupt ), 7.341 + .reg_busy (reg_busy ), 7.342 + .reg_bt3 (reg_bt3 ), 7.343 + .reg_bt2 (reg_bt2 ), 7.344 + .reg_bt1 (reg_bt1 ), 7.345 + .reg_bt0 (reg_bt0 ), 7.346 + .reg_s_con (reg_s_con ), 7.347 + .reg_d_con (reg_d_con ), 7.348 + .reg_incw (reg_incw ), 7.349 + .reg_inchw (reg_inchw ), 7.350 + .reg_rdelay (reg_rdelay ), 7.351 + .reg_00_data (reg_00_data ), 7.352 + .reg_04_data (reg_04_data ), 7.353 + .reg_08_data (reg_08_data ), 7.354 + // system clock and reset 7.355 + .CLK_I (CLK_I ), 7.356 + .RST_I (RST_I ) 7.357 + ); 7.358 7.359 - //Master control 7.360 - MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH), 7.361 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL( 7.362 - //master read port 7.363 - .MA_ADR_O (MA_ADR_O ), 7.364 - .MA_SEL_O (MA_SEL_O ), 7.365 - .MA_WE_O (MA_WE_O ), 7.366 - .MA_STB_O (MA_STB_O ), 7.367 - .MA_CYC_O (MA_CYC_O ), 7.368 - .MA_CTI_O (MA_CTI_O ), 7.369 - .MA_LOCK_O (MA_LOCK_O ), 7.370 - .MA_DAT_I (MA_DAT_I ), //32bits 7.371 - .MA_ACK_I (MA_ACK_I ), 7.372 - .MA_ERR_I (MA_ERR_I ), 7.373 - .MA_RTY_I (MA_RTY_I ), 7.374 - //master write port 7.375 - .MB_ADR_O (MB_ADR_O ), 7.376 - .MB_SEL_O (MB_SEL_O ), 7.377 - .MB_DAT_O (MB_DAT_O ), //32bits 7.378 - .MB_WE_O (MB_WE_O ), 7.379 - .MB_STB_O (MB_STB_O ), 7.380 - .MB_CYC_O (MB_CYC_O ), 7.381 - .MB_CTI_O (MB_CTI_O ), 7.382 - .MB_LOCK_O (MB_LOCK_O ), 7.383 - .MB_ACK_I (MB_ACK_I ), 7.384 - .MB_ERR_I (MB_ERR_I ), 7.385 - .MB_RTY_I (MB_RTY_I ), 7.386 - //register interface 7.387 - .M_SEL_O (M_SEL_O ), 7.388 - .reg_start (reg_start ), 7.389 - .reg_status (reg_status ), 7.390 - .reg_interrupt (reg_interrupt ), 7.391 - .reg_busy (reg_busy ), 7.392 - .data_length (data_length ), 7.393 - .reg_cntlg (reg_cntlg ), 7.394 - .reg_bt2 (reg_bt2 ), 7.395 - .reg_bt1 (reg_bt1 ), 7.396 - .reg_bt0 (reg_bt0 ), 7.397 - .reg_s_con (reg_s_con ), 7.398 - .reg_d_con (reg_d_con ), 7.399 - .incr_unit (incr_unit ), 7.400 - .reg_00_data (reg_00_data ), 7.401 - .reg_04_data (reg_04_data ), 7.402 - //system clock and reset 7.403 - .CLK_I (CLK_I ), 7.404 - .RST_I (RST_I ) 7.405 - ); 7.406 + // Master control 7.407 + MASTER_CTRL 7.408 + #(.MA_WB_DAT_WIDTH (MA_WB_DAT_WIDTH), 7.409 + .MA_WB_ADR_WIDTH (MA_WB_ADR_WIDTH), 7.410 + .MB_WB_DAT_WIDTH (MB_WB_DAT_WIDTH), 7.411 + .MB_WB_ADR_WIDTH (MB_WB_ADR_WIDTH), 7.412 + .S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 7.413 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 7.414 + ) 7.415 + MASTER_CTRL 7.416 + ( 7.417 + // master read port 7.418 + .MA_ADR_O (MA_ADR_O ), 7.419 + .MA_SEL_O (MA_SEL_O ), 7.420 + .MA_DAT_O (MA_DAT_O ), 7.421 + .MA_WE_O (MA_WE_O ), 7.422 + .MA_STB_O (MA_STB_O ), 7.423 + .MA_CYC_O (MA_CYC_O ), 7.424 + .MA_CTI_O (MA_CTI_O ), 7.425 + .MA_LOCK_O (MA_LOCK_O ), 7.426 + .MA_DAT_I (MA_DAT_I ), 7.427 + .MA_ACK_I (MA_ACK_I ), 7.428 + .MA_ERR_I (MA_ERR_I ), 7.429 + .MA_RTY_I (MA_RTY_I ), 7.430 + // master write port 7.431 + .MB_ADR_O (MB_ADR_O ), 7.432 + .MB_SEL_O (MB_SEL_O ), 7.433 + .MB_DAT_O (MB_DAT_O ), 7.434 + .MB_WE_O (MB_WE_O ), 7.435 + .MB_STB_O (MB_STB_O ), 7.436 + .MB_CYC_O (MB_CYC_O ), 7.437 + .MB_CTI_O (MB_CTI_O ), 7.438 + .MB_LOCK_O (MB_LOCK_O ), 7.439 + .MB_ACK_I (MB_ACK_I ), 7.440 + .MB_ERR_I (MB_ERR_I ), 7.441 + .MB_RTY_I (MB_RTY_I ), 7.442 + // register interface 7.443 + .reg_start (reg_start ), 7.444 + .reg_busy (reg_busy ), 7.445 + .reg_status (reg_status ), 7.446 + .reg_interrupt (reg_interrupt ), 7.447 + .reg_bt3 (reg_bt3 ), 7.448 + .reg_bt2 (reg_bt2 ), 7.449 + .reg_bt1 (reg_bt1 ), 7.450 + .reg_bt0 (reg_bt0 ), 7.451 + .reg_s_con (reg_s_con ), 7.452 + .reg_d_con (reg_d_con ), 7.453 + .reg_incw (reg_incw ), 7.454 + .reg_inchw (reg_inchw ), 7.455 + .reg_rdelay (reg_rdelay ), 7.456 + .reg_00_data (reg_00_data ), 7.457 + .reg_04_data (reg_04_data ), 7.458 + .reg_08_data (reg_08_data ), 7.459 + // system clock and reset 7.460 + .CLK_I (CLK_I ), 7.461 + .RST_I (RST_I ) 7.462 + ); 7.463 + 7.464 endmodule // WB_DMA_CTRL 7.465 `endif // WB_DMA_CTRL_FILE